Thread by @PatrickMoorhead

Intel "P" Core:
-"performance" CPU core
-adds FP16 ML accel to AVX512
-claims 19% advantage over 11th Gen based on SPEC, Sysmark, Crossmark, PCMark, WebXPRT3, Geekbench
-Adds new "AMX" matrix engine for DL inference and training (?) claims 8X improvement on int8 (SR only)
$INTC

Thread Director does exactly what you would expect. It manages threads that:
-should go on P-core
-should go on E-core
-should move from P to E-core
If you recall early vers of Arm big.LITTLE had early issues with thread mgmt. Intel claims it's ahead of everyone on this. $INTC

Intel's Alder Lake (client) proc:
-spans ultra-portable (9W) to DT (125W)
-monolithic design, 3 pkg
-Up to 16C (8P/8E), 24T (16P/8E), 30MB cache
-DDR5, PCIe 5, WiFi6, Xe, TB4,
-Neither F or perf disclosed, but at min expect to be comp in notebook & <16T DT
-AI perf ?
$INTC

Intel's Sapphire Rapids (datacenter) proc:
-focused on node *and* DC perf (smart positioning)
-distributed design (tiles + package, more like AMD), each thread can access all tile resource
-all P cores (see above for deets)
$INTC

Like ICL, Sapphire Rapids has lots of acceleration, but better:
-Data streaming
-Crypto
-Compression, decompression
-AI
Now, how do you feed this beast?
$INTC

Sapphire Rapids is distributed design, many CPU cores, many acceleration blocks, how do you feed it and extract results?
-I/O: CXL 1.1, PCIe 5.0, UPI 2.0
-Cache: >100MB LLC, 8CH DDR5, Optane 300
-HBM2: 1TB/sec
$INTC

Intel didn't officially announce SR, so no deets on core count, frequencies, BUT Intel did share a few nuggets on accel (see above) plus:
-AI: AMX vs AVX FP32, BF16, INT8
-Microservices: SR vs CL vs ICL (cool!)
Net-net, right now expect really good perf in accel workloads.
$INTC

Intel announced "Mount Evans" IPU:
-ASIC-based (vs FPGA)
-best expl yet of IPU (or NV/Marvell DPU) & SmartNICs (bravo)
-ME IPU co-developed with "major CSP"; guessing Azure given FPGA work
-Compute Engine Arm Neoverse N1-based (surprise!)
Hard to gauge competitiveness.
$INTC