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4 May, 26 tweets, 31 min read
@binarydebt @pencan94 @aschilling @MoStueck I assume the times can be explained like that, for 686DLC Distributed Core WMAN 32+16**2 Bit CPU
R16 P32 S16
ENQ JMP1 INT
RTS REQ1 CTS
PUT GET1 GET *L1HIT 3
CHK JMP2 ENQ
ENQ CMP2 CHK *L2MIS 5
CTS REQ2 RTS
GET GET2 PUT
ENQ JMP1 CHK *L2ECC 8
CHK REQ1 ENQ
ACK GET1 ACK * L2HIT 10
@binarydebt @pencan94 @aschilling @MoStueck Thought merged here for the tweet, so think of two of such DSP unit as a cluster, where receive unit belongs to unit 0b0000 and send unit belongs to unit 0b0001 and the instructions are of course distributed (marked with 1 or 2 decimal above) and certainly each unit SEND'N'RECV.
@binarydebt @pencan94 @aschilling @MoStueck And L3 at 16 threads (&2],3,4,..) at L1MIS
ENQ JMP ENQ XXX JMP INT XXX NOP XXX
RTS CMP CHK ENQ REQ CTS XXX JMP INT
XXX REQ XXX RTS NOP XXX ENQ REQ CTS
XXX NOP XXX MRG NOP XXX ACK GET PUT
MRG GET PUT ACK GET PUT XXX JMP ACK
ACK JMP ACK XXX JMP ACK XXX NOP XXX
@binarydebt @pencan94 @aschilling @MoStueck despite mixed Send Side (depicted left) and Receive Side (depicted right) in first picture, following such scheme for all the remaining remote 14 cluster nodes, we see the 2nd thread of the unit under observation here start at cycle 4 and works additionally in 5, 6, 32, 3 (use:8)
@binarydebt @pencan94 @aschilling @MoStueck and all the other threads belonging to cluster as a node-pair are addressed on a node basis instead of pair basis, so each consumes 4 cycles and add 2 cycles to overall time for L3 access. Resulting in the 33 overall. Each node also involves 4 cycles in its send and receive unit.
@binarydebt @pencan94 @aschilling @MoStueck So threads 16&1 are additionally connected like at cycle 20,21,22 (additionally shown context 17-19):
XXX JMP INT XXX NOP XXX
ENQ REQ CTS XXX NOP XXX
ACK GET PUT XXX NOP XXX
[ENQ] JMP ACK XXX [JMP] [INT]
[ACK] NOP XXX [ENQ] [CMP] [ACK]
XXX NOP XXX [ACK] [JMP] XXX
@binarydebt @pencan94 @aschilling @MoStueck ENQ JMP XXX XXX NOP INT
RTS REQ XXX XXX NOP CTS
PUT GET XXX XXX NOP GET *L1MIS 3
CHK NOP XXX ENQ JMP ENQ
ENQ NOP XXX RTS CMP CHK *L2MIS 5
XXX NOP XXX XXX REQ XXX
XXX NOP XXX XXX NOP XXX *x13 7-19*x9 23-31
MRG REQ XXX MRG GET PUT
ACK GET XXX ACK JMP ACK *L3HIT 33
@binarydebt @pencan94 @aschilling @MoStueck XXX JMP INT XXX NOP XXX *L3MIS 20
ENQ CMP ACK XXX NOP INT
ACK JMP XXX XXX NOP ACK *L3ECC 22
So on primary node of primary unit that issues request for L3, we count 8 main, 9 send and 2 receive circuit use and 3 more JMP to imply if not idle and the NOPs to be used to...
@binarydebt @pencan94 @aschilling @MoStueck Or 4 main, 5 send, 1 receive and 2 more JMP if not idle for L3MIS detection after 20 cycles... Or 6 main, 7 send, 2 receive on L3ECC after 22 and 3 more JMP if not idle... Thought could find HA error at different stages (steps 1-5, 21, 22, 32, 33).
On slave node of primary unit,
@binarydebt @pencan94 @aschilling @MoStueck .. we count 5 main, 4 send, 9 receive, 3 more JMP if not idle, involved over the length of 30 cycles in main but all 33 in the WMAN units, could bail out at 6, 21, 22, 32, 33, where 6 would be noticed at 20 (means if node 0xF is not Enquiring).
So an L3 lookup involves 14 auxill-
@binarydebt @pencan94 @aschilling @MoStueck ... ary cluster nodes each 4 main, 4 send, 4 receive cycles and on 13 nodes 2 additional JMP cycles possible where at node 0xE this makes no sense, only if speculating for an L3 Error detected in cycle 20-22 on primary pair or 18-20 at node 0xF. Makes a maximum use of 56+26=82
@binarydebt @pencan94 @aschilling @MoStueck .... main, 56 send, 56 receive, 8+3=11 main, 9 send, 2 receive on primary primary and 5+3=8 main, 4 send, 9 receive on slave primary.
Over all that means 69+32=101 main, 69 send, 67 receive actions overall. In terms of the communication-adaptor with each 16 bits using 32 YAGNIbit
@binarydebt @pencan94 @aschilling @MoStueck ..... of a 64bit hardware redesigned for that very special purpose, some multiplexing is possible. For calculation: 128 64bit processors power available for 16 node fleet. Means for each node, means about 8 real 64bit CPUs in background serving each node. 1 dedicated send-adapter
@binarydebt @pencan94 @aschilling @MoStueck ...... and 1 dedicated receive-adaptor each 64 bits, means 96 bit power remaining after pure communications counter parts can be used out of the 2*64 bit, leaving 32 bit for security functions as encryption and checksumming and -checking for both unit parts (implemented 1*64bit).
@binarydebt @pencan94 @aschilling @MoStueck ....... and a 32 bit virtual cpu remaining on the same kind virtulized 64 bit CPU as on the nodes, act as a counter-node to stabilize or autodrive the served node, based on the served nodes capacity. Three more CPUs are implemented as 3x16 core unit, responsible for MA-Calcula-
@binarydebt @pencan94 @aschilling @MoStueck ........ tion for a fleet, and and another 48 cores are built as a 24 core CPU as master (serving a class A (/8) net together with further such CPUs for as many /28 networks assigned to that range), a 16 core CPU as local master (serving a class B (/16) net, again as many of such
@binarydebt @pencan94 @aschilling @MoStueck ......... CPUs as there are /28 networks officially assigned to that B-net) and an 8 core CPU acting as gateway centered over the up to 16 fleet units with each 3*16 core asitance mentioned first sharing that particular class C (/24) net on the first 4 bit of that address space.
@binarydebt @pencan94 @aschilling @MoStueck .......... All that spoken primarily in terms of empirical PANTHER DSP. For each DSP core the two cores supplying the 64 bit security, 2x16 bit communication and the 32 bit virtual counternode for each node are 1x16 core, 2x4 core, 1x8 core AXI host (node assistance partitions).
@binarydebt @pencan94 @aschilling @MoStueck The further 3x16 core shared MA-Calculation is the DMA controller for the cache-less DSP cores, one serving as L1, L2, L3 cache providing memory access controller, connected by the 8 core FPU centering with the SecCommCounter AXI host assistances, providing FastInterConnect.
@binarydebt @pencan94 @aschilling @MoStueck .. That having the /28 network assigned to a SPEED PANTHER DSP SoC, where the FPU unit interconnecting and defining address-range also provide a low-latency-interconnect to other possible units within that range, such as SPEED RAPTORs, CHAMAELEON (three different BAT kinds) and
@binarydebt @pencan94 @aschilling @MoStueck ... SPIDER (more only one BAT kind but in fact at least two kinds of BAT connected here). SPIDER also act as the representative class B (/16) network controller as 16 core CPU is the TCM controller and the 24 core Processor is feeding the ULP i$ component as class A (/8) level
@binarydebt @pencan94 @aschilling @MoStueck .... standin responsible for a PANTHER within that class A network and also for the TCM which consolidates also the CHAMAELEON and takes care for with them for the direct SPEED-class interconnection performance, where these units (class C members belonging to respective group of
@binarydebt @pencan94 @aschilling @MoStueck .... SPIDER TCMs or type B CHAMAELEON or SPIDER BATs) together with the ULP i$ class A controlers (BAT handling analog digital converts, type A works as type C CHAMAELEON bi-directional influenceand type B is the ADConverter acting mainly through SPIDER as BAT type B) and also
@binarydebt @pencan94 @aschilling @MoStueck ..... the most native type A BAT CHAMAELEONS take part in regulating and providing the Event Unit. All together on the well designed Maestro-Platform which cares for the interoperatibility and finaly for the successfull and sutainable ML/AI accellerating technology, represented.
@binarydebt @pencan94 @aschilling @MoStueck So just to note: The simple ACK means, as for all is, even for men with their BATs that are not digital but human still and forever (at least as soon as the eveils sins are stopped completely soon), means an Update so Notice (signed or checksummed) to the ETC Smart-Contract SYS.

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