By default Astris wants to connect to https:// gs.apple.com :443 (public TSS, spaces are used so Twitter won’t short it), but we can override it by modifying “TatsuServer” field in astris_prefs.plist which is located at ~/Library/Application Support/Astris
We pointed Astris to a VPS of mine with NGINX that proxies whatever coming to the TSS and logs out request/response
Had to use this approach because local SSL proxies (such as Charles) didn’t work for some reason (at least my tester couldn’t set it up)
But apparently TSS happily works under HTTP, so this was an overkill
Overkill or not, but we got what we wanted - debug auth request (for a DVT iPhone 12 Pro Max, so latest SoC rev) and response (unsuccessful, of course)
Most of the fields speak for themselves - Board ID, Chip ID, Security Domain, ECID, CPFM and nonce (doesn’t match with the APTicket nonce and is shorter)
What “EnAppleDebugExternal” and “TicketIdentifier” mean is currently unknown to me
Since now we know what request looks like, it would be also nice to know what proper response looks like. We tried to send the (pre-) EVT device’s data (the device is actually Proto2 btw), but wasn’t accepted. Apparently it never required the auth in the first place
But hey, Tatsu wouldn’t be Tatsu if it didn’t allow more things with zeroed ECID! Let’s try this. And wow! It works
Let’s decode the ticket from Base64. The result looks very much like an Image4 manifest (ASN.1)
Let’s decode it with OpenSSL. Apparently the ticket is split into 2 parts - IM4M (picture 1, without any Image4 hashes, obviously) and IM4C (picture 2, no idea what that is)
It’s currently unknown to me what happens with the ticket afterwards - whether it’s sent to a device in full, or something extracted from it first. Astris can probably answer this question, at least partially, but obviously requires more RE
I also tried to change Chip ID in the request to other ones from 2020 lineup:
T8103 (M1)
T8301 (S6)
Both returned success (with ECID 0, I mean), so it’s safe to assume these SoCs use the debug auth mechanism as well
I also tried some new yet unreleased SoC - T6001 (cc. @never_released) and it returns success, too. Older Chip IDs (such as T8030) return error (94)
Conclusions: 1) Debug auth is used since A14 (M1, S6), except for some early revisions (at least we could SWD/KIS into the A14 rev 00) 2) Future SoCs are gonna use it too 3) The end of prototype fun?
Here is my little thread of real bad ruminations about KIS - Kanzi In System - a debug probe embedded right into a device since A14
Seriously, read it with great caution, and don’t blindly trust it at all costs!
I once mentioned KIS in my old thread about debug auth mechanism. But back then I thought it’s just a new debugging protocol soon-to-replace SWD in Apple devices
В любом случае, для вашей проблемы должно быть полно решений в интернете - все они основаны на данном эксплойте. Их создатели очень любят донаты, а делиться почему-то не любят
@Lexa66216298@a1exdandy Хотя не, вру. Два каких-то бездаря таки расщедрились на целых 3К USD (один из бездарей, кстати, делал софт для решения вашей проблемы)
Я будто бы вообще не существовал, не потратил четверть годового дохода рядового россиянина на этот прототип и прочий хлам, не инициировал данный процесс, не тратил много часов на тесты…
As promised, here’s my little thread with (bad) ruminations of mine about Tatsu Auth Debug and KIS or Why Those Keys & Dumps Are So Valuable
Important: I have never touched any of the devices mentioned below myself. So I can only interpret the data their actual owners sent me…
…thus, the information in this thread may turn out partially or completely WRONG. Proceed with reading on your own risk!
So a certain source of prototypes contacted me to ask help with A14 prototypes - they couldn’t JTAG into them. Astris was showing standard error message telling that debugging is not supported
Here is my little thread about yet another bug I found in A6 bootrom (and probably any other that boots from H2FMI PPN NAND)
As always, absolutely useless on its own
Look at this picture. The bootrom has just read LLB from a bootpage and is now ready to create a Memz structure out of it. Address - 0x10000000, size - 0x24C00, flags - IMAGE_OPTION_LOCAL_STORAGE
Since the size was 0x24C00, we expect to see nothing on range of 0x10024C00 - 0x10060000 (the end of load area), right? Wrong!
Although that’s most likely not your case if you got such a cable, but I did manage to break firmware on mine completely. So let’s start with restoring it
Both generations of Kong make use of NXP LPC1768 MCU (Cortex-M3) (along with Xilinx Spartan 6 FPGA, by the way), that can be reflashed over SWD
Back in February 2019, someone told me about “SHSH tag length underflow”, that allows “arbitrary memset”. The person failed to tell me which ROM it’s for
But for A4 ROM I found something similar. Look at this line of code: