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A BIG SUCCESS!
I've just found the right combination of #DisplayPort Transfer Unit (TU, aka "Packet Size") and Pixels per TU to allow standard 720p pixel clock down a single DP lane (and #FullHD down two lanes) - 40 bytes, with 11 pixel.
Life has become easy....
I've just found the right combination of #DisplayPort Transfer Unit (TU, aka "Packet Size") and Pixels per TU to allow standard 720p pixel clock down a single DP lane (and #FullHD down two lanes) - 40 bytes, with 11 pixel.
Life has become easy....
Sorry, just having a major #nerdgasm here.
I've been playing with #FPGA #DisplayPort and for a few years, and I have metaphorically found the keys to easy implementation of standard 720p & 1080p video while pulling weeds in the garden.
I've been playing with #FPGA #DisplayPort and for a few years, and I have metaphorically found the keys to easy implementation of standard 720p & 1080p video while pulling weeds in the garden.
Now I have a #FirstNerdProblem... work on this tonight or watch the @spacex launch?
