Discover and read the best of Twitter Threads about #KiCad
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💥Day 1: Doom iCEBreaker Edition
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
@1bitsquared ⛵️Day 2: VexRiscv FPU
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
