Thread by @carlosedp

I'll start a "live-tweet" thread for the process to add @DigilentInc ArtyA7 support to my @chisel_lang ChiselBlinky project including FuseSoc support.
This is inspired by @OlofKindgren thread yesterday.
Follow the 🧵

@DigilentInc @chisel_lang @OlofKindgren Disclaimer, I've never used Xilinx FPGAs and Vivado and will discover how to use it as I go. I currently have a Windows 10 VM with Vivado installed.
Later I'll setup a Linux VM with it as recommended by @mithro and @hasheddan and also try with @YosysHQ stack.

@DigilentInc @chisel_lang @OlofKindgren @mithro @hasheddan @YosysHQ Blinky expects five IO pins, a clock input, a reset button and three leds.
The clock is fed into a PLL to generate a 25Mhz output. The PLL is normally a blackbox that wraps the vendor PLL IP in Verilog added to the resources folder.

I'll grab the ArtyA7 35T master constraint file that contains all the pinout for this board. It's on @DigilentInc Github at github.com/Digilent/digil…
We'll use:
Clock: E3
Reset: D9 (btn0)
Led0: H5
Led1: J5
Led2: T9

@DigilentInc There we go. We have the constraints file.
ChiselBlink expects the PLL Verilog to live in the src/main/resources dir named as "pll_boardname.v".
We will call this board artya7-35t. I could open Vivado, browse it's IP library to generate the PLL.

@DigilentInc Since I'm lazy, I'll borrow an existing PLL Verilog from @OlofKindgren CoreScore and change the output clock. The Arty has a 100Mhz osc. From what I see, the PLL divides the clock by 100 and multiplies by 16 (for CoreScore). I'll change to 25 and adjust module and pin names.

Nice, right now we can generate Verilog code from @chisel_lang.
Both Toplevel.v and our PLL are in the 'generated' output dir.
asciinema.org/a/407028?speed…

@chisel_lang Now adding FuseSoc support. It's a matter of three sections, the static files (only the constraints in this case), the chisel-generator that generates Verilog from Chisel and the target that has the EDA tool (Vivado) and FPGA part. Also it's where we link it all together.

In the generator section, we have listed the files our Chisel generator outputs. Here it's the Toplevel.v with Topmodule and Blinky modules and another file with the PLL module. Since we used a blackbox, Chisel creates a separate Verilog file for it. We add both.

Here we create the FuseSoc project, add the libraries (both Fusesoc-cores that contains the generator and the local library with chiselblinky).

asciinema.org/a/407036?speed…

In the end we have the complete project to be opened on Vivado.

Now, going to my Windows 10 VM (it's a VirtualBox VM so I can share folders between my Mac host and it) I'll open a command prompt and load Vivado environment. Then I'll go to my project dir containing the files.

I'll run the command:
"vivado -notrace -mode batch -source carlosedp_demo_chiselblinky_0.tcl" to generate the project file. Then open the resulting file with Vivado GUI with:
"vivado carlosedp_demo_chiselblinky_0.xpr"

If I was running on Linux, the Makefile would automate this.

I'm going manually on these steps but FuseSoc generates TCL scripts to do it.
I'll run Synthesys using the play button on the toolbar.

When finished, Vivado will ask me what to do. I chose "Run Implementation".

Just as a heads-up, since I'm running this on a VM, I passed my board that is connected thru USB to the VM via the toolbar setting in VirtualBox.

Probably my lazyness and PLL strategy didn't work out as expected. Let's fix this.

Great opportunity to learn how to use the Clocking Wizard.
Input 100Mhz, output 25Mhz, no reset out, lock out.

With a ton more Verilog code, we have our PLL.

Let's re-run the whole fusesoc run step to generate the files and load into Vivado.

Then, let's generate the bitstream.. BTW I love stats... my design uses 8 LUT and 25 FlipFlops 😃

After Bitstream is done, lets open the Hardware Manager, Open the target (choose auto-connect) and program the board.
Some nice sensor stats shown as well.

Weirdly enough, Vivado doesn't "auto-load" the generated bitstream. I had to manually find it on the .runs/impl_1 directory.
Again, this might be me not knowing how to use it properly. 😬

And there we have it, running and blinking. One minor gotcha is that this board switches are not inverted logic so I'll add this handling to my Toplevel module. Here I'm holding the reset button.

As soon as I have the code cleaned up, It will be pushed to the repo at: github.com/carlosedp/chis…

Thanks for following this thread. I hope it was resourceful for you as it was for me.
Also send me feedback if this style of tweeting is valuable!

The code has been pushed and is on Commit:
github.com/carlosedp/chis….