Thread by @IanCutress

#VLSI22 pt1:
Intel 4 update:

EUV + FinFet
50nm gate pitch
30nm fin pitch
40nm min metal pitch
16 metal layers
Enhanced Copper at lower layers for lower line resistance
8 VT options (4N+4P)

Claims of 2x area scaling of HP logic library, plus +20% perf at iso-power over Intel 7.

#VLSI22 Thread Part 2:
Also from Intel, Low power 6T SRAM on Intel 4:

Old 6T design:
5.8x power at 23.8 Mb/mm2
Old 8T design:
1.0x power at 13.7 Mb/mm2
New 6T design:
1.03x power at 19.4 Mb/mm2

TL;DR can now offer low power SRAM at better density. No word on latency

#VLSI22 Thread Part 3:

@IBM demonstrates 216Gb/s PAM8 with 288 mW power consumption on 4nm FinFET.

#VLSI22 Thread Part 4:

TSMC showcase Bismuth-assisted fabrication of high-perf WS2 monolayer transistor deposition via CVD. A 2-inch section of a 4-inch SiNx wafer with Sb/Au contacts.

Aka 2D transistors still in research phase.

Just to add here, this is a continuation of the Bismuth paper from last year that *STILL TO THIS DAY* gets misquoted as '1nm transistor paper'. It's not. It was nothing to do with 1nm transistors. It was all to do with parts of a transistor working together. Read the damn thing.