Discover and read the best of Twitter Threads about #VLSI22
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#VLSI22 pt1:
Intel 4 update:
EUV + FinFet
50nm gate pitch
30nm fin pitch
40nm min metal pitch
16 metal layers
Enhanced Copper at lower layers for lower line resistance
8 VT options (4N+4P)
Claims of 2x area scaling of HP logic library, plus +20% perf at iso-power over Intel 7.
Intel 4 update:
EUV + FinFet
50nm gate pitch
30nm fin pitch
40nm min metal pitch
16 metal layers
Enhanced Copper at lower layers for lower line resistance
8 VT options (4N+4P)
Claims of 2x area scaling of HP logic library, plus +20% perf at iso-power over Intel 7.
#VLSI22 Thread Part 2:
Also from Intel, Low power 6T SRAM on Intel 4:
Old 6T design:
5.8x power at 23.8 Mb/mm2
Old 8T design:
1.0x power at 13.7 Mb/mm2
New 6T design:
1.03x power at 19.4 Mb/mm2
TL;DR can now offer low power SRAM at better density. No word on latency
Also from Intel, Low power 6T SRAM on Intel 4:
Old 6T design:
5.8x power at 23.8 Mb/mm2
Old 8T design:
1.0x power at 13.7 Mb/mm2
New 6T design:
1.03x power at 19.4 Mb/mm2
TL;DR can now offer low power SRAM at better density. No word on latency
