Thread by @jcawley01

Chip wars: How ‘chiplets’ are emerging as a core part of China’s tech strategy | Reuters

1/ I’ve posted on this many times. I suspect it will be the decisive front deciding the future of the semi industry. US and China start on even footing.
reuters.com/technology/chi…

2/ Here’s a thread explaining why this is such a big deal.

Everyone has heard of Moores law and knows it’s been the technical underpinning of the amazing success of the semiconductor industry. Each node - 90nm, 28nm, 14nm etc - is faster, denser and cheaper for everything.

3/ There were thousands of inventions reqd at each stage, but the underlying physics was driven by something called Dennard Scaling. That’s the physics that made smaller chips both denser *and* faster.

It reached its physical limits about 8 yrs ago. It’s over.

4/ Semiconductor engineers have continued to find ways of shrinking transistors and packing them more densely on a chip, but without Dennard scaling they no longer run faster. They’re *just* denser. So how do you get more speed?

5/ At one level you don’t. That ride, the one that’s propelled the industry since it’s inception, is over. Done. Has nothing to do with US financialization nor China’s rise. It’s not an engineering limit it’s a physical limit.

So, how has the industry responded?

6/ The first step was to use the added density to put multiple cores on a chip. Each core is basically its own computer. Going from a single core chip to a double core means you went from one computer of speed X to two computers, both running at X.

7/ Of course you could just buy two of the older model computers and have had the same total capacity and speed. However that slows the communication between the two computers so if there’s a lot of inter-processor data it might be slower than on a single chip, in some cases.

8/ That makes speed a function of specific workload characteristics. There’s a fork in the road. One the semi industry never use to worry about. Monolithic algorithms can’t get any speed advantages. If you have a lot of them, like a lg server, you can run them in parallel.

9/ But if they’re truly monolithic it’s not really that different from just having more of an older generation. (There actually are some advantages but they’re not huge, nor does the advantage itself scale.) Still, that’s the easiest path and kept things going for several yrs.

10/ For non-monolithic workloads, one’s where many sub tasks can be split out, run in parallel, and get useful advantages from shared cache & memory, we can use the multiple cores to speed those up.

So, what works like that?

Many engineering analyses, simulations & AI training

11/ Those are very important but kind of limited. They’re also very complex to make work in a way that the theoretical advantages are realized. And, it takes coordination between HW design and SW algorithms.

That’s big & important but also very narrow.

12/ The other trick is to create customized cores and/or accelerators tuned to optimize very specific workloads. Engineers carefully map instruction patterns looking for common structures to optimize. It’s hard, expensive and a slow process. Need very in-depth details.

13/ The last major way to use added chip density to bring external semi processors onto the “main” chip. That can bring some useful performance though these days it’s mainly used to reduce costs.

14/ We’ve been able to exploit low hanging fruit in all these areas to sustain the effectiveness of Moores law since the ending of the Dennard scaling. However, that’s running out. Costs are going way up but *value* is in danger of flattening for most of the industry.

15/ We only get density, not speed, and the very potential to get value from that density is requiring more and more workload specific tuning and circuits. The value potential of general purpose chips is flattening.

16/ The key to future semi leadership is shifting from pushing the envelope on gp chips to optimizing parallel processing and acceleration of specific workloads.

The key isn’t going from 14nm to 7nm to 5nm. That path is expensive with little value.

The key is chiplets.

17/ Chiplets enable flexible production and assembly of workload optimized chips which is where *all* the future value of semiconductors will be invented.

The basis of competition in this arena begins to resemble the SW industry. Ecosystems will determine leadership.

18/ Defining an open innovation platform, with technical and commercialization enablement, the hallmark of SW competition, is becoming the key to semiconductor leadership. Intel, Samsung, TSMC all know this and have their strategies.

19/ But their strategies are rooted in process roadmaps which don’t actually contribute anything other than density and escalating costs. There are other strategies available that build off 14nm FinFET, the last “Dennard node,” and focus exclusively on packaging and chiplets.

20/ Enter China. As described earlier, workload optimization takes deep internal visibility of path lengths, parallelism and other technical characteristics. China has more of that in more sectors than anyone. The greatest potential for a new HW ecosystem is in China.

21/ Before our embargo, I put the odds of the specific shifts in this thread driving a shift in industry leadership at maybe 25%. The shifts are deep and at the heart of the value proposition but incumbency is very strong and it’s all very complex.

22/ Now, I’d put those overall odds closer to 50% and we’ve raised the odds that China will emerge as either *the* leader or “a” leader of this future.

Advanced chips are no longer faster, they’re denser and the value in that density comes from workload optimization, not litho.

23/ As this article makes clear, China knows this and has begun making it central to their strategies. As the cliche goes, theyre skating to where the puck is going. That said, it’s impossible to overstate how much this industry relies on global access to talent which remains key