LaurieWired Profile picture
May 23 4 tweets 3 min read Read on X
I miss the insanity of 80s processor design.

Intel’s iAPX 432 was a “micromainframe”.

It had no general purpose registers, supported object orientation *directly*, and performed garbage collection on-chip.

It was also 23x slower than an 8086. Here's why it failed. Image
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Intel targeted Ada so aggressively that C support was an afterthought.

Problem was, particularly at the time, the Ada compiler was extremely untuned and immature.

Scalar instructions were basically never used; *everything* was huge object-oriented calls. Image
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The “micromainframe” moniker wasn’t just marketing. One I/O chip could stitch together 63 CPUs on a single bus.

Essentially memory safe in-hardware; dangling pointers were impossible at the ISA level.

Partners like BiiN suggested using the CPU for nuclear-reactor control. Image
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Although the iAPX 432 was a commercial flop, the design lineage was appealing to unique, military applications.

Huges Aircraft used 35 i960 MXs (a rad-hard RISC chip birthed from the 432) for the main avionics of the F22.

The equivalent of 2 Cray super-computers on a single aircraft!

If you’d like to learn more about this unique ISA, check out Ken Shirriff’s blog. He goes into great detail about the history of the i960 design, and the 432 roots:
righto.com/2023/07/the-co…Image
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More from @lauriewired

Aug 6
Ring 0 is a highly-privileged state on CPUs.

Negative Ring Levels have even *higher* privilege. You just haven’t heard of them.

For X86, Ring -1 is Hardware Virtualization, Ring -2 is System Management Mode, Ring -3 is Intel ME / AMD PSP.

Arm get's even weirder: Image
Image
Negative rings are mostly due to X86 being really old; as the ISA got more complex, we got "above 0" states.

Armv8 moves in a positive direction; higher numbers have more privilege. From EL0 (user space) to EL3 (State-Switching).

Apple does something extra funky: Image
Image
For Apple’s M-chips, two substates were added to EL1+EL2, called GL1 and GL2.

During their reverse engineering efforts, Asahi Linux confirmed that the EL3 state doesn’t exist on the M1.

GL1 is a sandbox that the XNU kernel “jumps” into every time it edits a page table. Image
Read 4 tweets
Aug 2
An early rule you learn in computer science is:

“Never store currency as floats”

Nearly every popular language has special, built-in types for money. But why?

The *majority* of money-like numbers have no float representation, accumulating to massive errors over time: Image
Image
Go ahead and try this. Let’s add three dimes. Open up a python terminal, and type in:

0.10 + 0.10 + 0.10

Uh oh. See that little remainder?

It may seem trivial, but this mistake happens more often than you’d expect! Image
iBit, a Bitcoin exchange, encountered a “free money” glitch for this reason.

Orders were parsed as floats; you could create an order smaller than a single satoshi (minimum unit of Bitcoin).

Source wallet would round down (no change), target wallet rounded up (+1 satoshi). Image
Image
Read 4 tweets
Jul 30
Programming Languages used to be designed as powerful as possible.

Maximum possible utility given hardware constraints.

The pro move is to choose the *least* powerful, non-Turing-complete solution.

The entire web exists because of the Principle of Least Power: Image
Image
Don’t take my word for it. Tim Berners-Lee (inventor of HTML, HTTP, etc) had this to say:

“the less powerful the language, the more you can do with the data...”

HTML is purposefully *not* a real programming language.

The constraint pushed innovation to data processing. Image
Imagine an alternate-reality Web, where HTML didn’t exist.

Java applets would have been a serious contender; they certainly allowed for rich interactivity.

Yet, without a way to freely scrape simply formatted data, search engines would be a non-starter. Image
Read 4 tweets
Jul 29
When you make a Bank ACH transaction, it’s literally just an SFTP upload.

Sent as a NACHA file, it's 940 bytes of ASCII text.

Bank-to-Bank transactions cost ~0.2 cents. As long as it travels via encrypted tunnel; it’s compliant!

Here’s how the quirky system works: Image
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Chase offers a sample NACHA file to look at.

Notice the rows padded with 9s. It’s an artifact of a 1970s rule about magnetic tape, "always fill the block".

To this day, total line count *must* be a multiple of ten; otherwise the bank will drop the transaction. Image
Image
Of course, larger Fintech firms (think Stripe) wrap it up with modern APIs, but SFTP is the default for most US Banks.

Hilariously, NACHA rules don’t clarify *how* transactions should be encrypted.

Only that “commercially reasonable” cryptography should be used. Image
Read 4 tweets
Jul 28
Intel’s not doing so hot lately. Meanwhile vendors are killing it at the RISC-V Summit in China.

One CPU got a specint2006/GHz rating of 10.4/GHz!

To put it in perspective, a i7-4790k (Haswell) scores 8.1/GHz.

RISC-V is hitting high-end desktop territory FAST: Image
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No one realizes how quickly a CPU supply chain; completely independent of western IP is progressing:

Not long ago RISC-V performance was a joke.

Now it’s trading blows with x86 and high end ARM!

In another generation or two it’s going to be a *serious* contender. Image
UltraRISC (the vendor with the high specint2006 score) is fabbing on a pretty old node; TSMC 12nm.

They don’t even have full vector support yet!

Imagine in a few years, a ~7nm chip /w full vector extensions.

China will have *fast* CPUs with no license chokepoints! Image
Read 4 tweets
Jul 22
Fading out audio is one of the most CPU-intensive tasks you can possibly do!

Values that get close (but not quite) zero, hit an underflow gap known as "Subnormal" range.

It’s a mathematical conundrum so tricky, both x86 and ARM made special CPU instructions just to handle it! Image
Image
In computer science, mathematical real numbers are approximated by floating-point representations.

For a single 32-bit float, the smallest “normal” positive we can hold is 1.17 × 10^-38

Tiny differences could get rounded off, leading to later Divide by Zero errors! Image
In the 80s, companies were fighting over the IEEE 754 (floating point) standard.

Intel wanted “good arithmetic”. DEC wanted to round off to zero.

As the most contested proposal, Intel suggested a “subnormal” routine, so that 32-bit floats gradually underflow. Image
Image
Read 5 tweets

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