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SemiAnalysis

@SemiAnalysis_

May 13

OSATs are usually seen as “boring” semiconductor companies. But we’ve been, and remain, bullish on Amkor ($AMKR) and ASE ($3711.TW). Why?
Because both sides of the OSAT model, Assembly & Test, are starting to shift in a meaningful way. (1/10) 🧵

Let’s focus on the first for now; Assembly.

Historically, packaging = low-margin wire bonding. Not exciting.
ASE once made up ~40% of $KLIC’s wire bonder business. After the COVID boom, capacity flooded the market and growth stalled. (2/10)

But something is changing.
KLIC is now seeing :
• 90%+ utilization in China
And guiding to:
• H2’26 China growth +15–20% vs H1
At the Chipbook we have been tracking wire bonder imports into China which are up +108% YoY in March. (3/10)

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SemiAnalysis

@SemiAnalysis_

May 12

Something to watch closely as the war in Iran drags on:

A very obscure part of the semiconductor supply chain, Naphtha, is potentially
becoming a quiet constraint on AI chips. (1/11) 🧵

Here is what the supply chain looks like:

An oil called Naphtha is shipped on giant tankers from Middle Eastern countries like Kuwait, UAE and Saudi Arabia by companies like Aramco (Saudi Arabia) or
ADNOC (UAE).

Then Integrated Japanese Chemical companies like Daicel and Toagosei and Korean petrochemical giants like LG Chem or Lotte Chemical "crack" it (break it down) in massive factories to create Propylene gas. (2/11)

Next chemical companies in either Japan or Korea convert the propylene gas into an ultra-high-purity liquid called PGMEA. PGMEA is the "workhorse" solvent for the photolithography process. (3/11)

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SemiAnalysis

@SemiAnalysis_

May 6

Earlier this year, Micron announced it would acquire PSMC’s P5 Tongluo fab in Miaoli, Taiwan—the process has officially begun.

At first glance, this looked like a straightforward legacy logic/memory fab acquisition. But the details worth a close look. (1/10) 🧵

The site has two key sections: Section A and Section B.

Section A already exists and is now being converted for likely Micron’s 1b DRAM process. Because it is not EUV-compatible, 1b is a practical fit for the existing cleanroom setup with proper equipment from Micron in coming quarters (the existing legacy equipment are from PSMC and those were not including in the acquisition agreement). (2/10)

Section B is different.

The cleanroom has not broken ground yet, so it is unlikely to come online before the end of 2027. But because Micron can design it from scratch, it should be built to support EUV and advanced HBM manufacturing. (3/10)

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SemiAnalysis

@SemiAnalysis_

Apr 10

Jensen showing Rubin Ultra as an MCM was the real tell. This is not just Nvidia gluing more dies together because it feels like the next cool architecture move. It is what happens when reticle limits, power density, yield, and package economics all start forcing the same answer. (1/5)🧵

For people outside packaging, here is the intuitive way to think about it. Chips do not move through OSAT as loose magical objects. They move through a very physical factory flow with trays, boats, carriers, sockets, test handlers, ovens, lid attach, mark, inspection, and shipping constraints. There are standard footprints for how packaged parts are handled. A common JEDEC tray is roughly 12.7 by 5.35 inches (322.6 × 135.9 cm) externally, and once your package starts eating too much of that real estate, everything gets uglier. Fewer units per tray. Worse mechanical margin. Harder handling. More custom tooling. More risk in test and burn-in. Higher cost everywhere. (2/5)

That is why Rubin Ultra matters. Jensen effectively showed Nvidia is getting close to the point where performance scaling is colliding with plain old package geometry. Once a package gets massive enough, the question is no longer just “can TSMC build the silicon?” It becomes “can the OSAT ecosystem move it, test it, cool it, assemble it, and yield it at scale without breaking the economics?” (3/5)

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SemiAnalysis

@SemiAnalysis_

Apr 3

Memory is taking over Hyperscaler CapEx.

In CY23 and CY24, memory was ~8% of total Hyperscaler spend. We estimate it hits 30% in CY26 and moves higher in CY27. That's a near-4x shift in just four years. (1/4) 🧵

What's driving it:
🟠 DRAM prices are expected to more than double in CY26, with another double-digit ASP increase in CY27
🟠 LPDDR5 contract pricing up over 3x since 1Q25. Price likely exceeds $10/GB in 1Q26 on the open market
🟠 HBM remains structurally undersupplied through CY27. AI-based servers already see significant % BOM costs from HBM, before price hikes
🟠 We know B200 server prices are going up 15–20% by year-end

Memory is a massive % of the $250B in incremental hyperscaler spend this calendar year. (2/4)

One dynamic the Street is missing:

NVDA receives VVP (Very Very Preferred) DRAM pricing, well below both hyperscalers and the broader market.

This compresses Nvidia's own server cost exposure and bends down overall market pricing, masking how severe the crunch really is.

AMD is on the other side of this trade. Their SKUs generally carry higher content, and AMD doesn't benefit from the same supplier pricing treatment. Structurally more exposed at a time when it operates at far lower AI accelerator scale. 👀 (3/4)

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SemiAnalysis

@SemiAnalysis_

Mar 26

CPO (Co-Packaged Optics) testing is critical because the cost of failure is enormous. Once an optical engine is attached to the switch package, a defect can jeopardize the entire assembly rather than a replaceable module. The CPO test flow follows four sequential phases, each with distinct technical challenges, equipment requirements, and vendor ecosystems. (1/5)

Phase 1 — Wafer-Level Single-Die Test: The EIC and PIC are tested separately at the wafer level before bonding. The EIC is standard CMOS wafer sort (no new equipment). The PIC requires novel double-sided electro-optical probing — this is where all the new equipment spend goes. (2/5)

Phase 2 — Double Side Wafer-Level Test (EIC + PIC): After the EIC and PIC are bonded together (via hybrid bonding, wire bonding, or flip-chip), the combined wafer is tested as an integrated E/O unit before dicing. (3/5)

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