Assembled the (v0.6) AKL-AV1 prototype! Characterization results in this thread.

For those of you just tuning in, the AV1 is an open hardware 1.5 GHz class, high impedance, solder-in, single ended active voltage probe (5MΩ || 350 fF, 10x attenuation) that runs on 5.5V DC. First step is low frequency trimming. This adjusts the DC path (OPA210) and AC path (BUF802) to have the same gain.

Seen here before and after.

Friend of mine has been troubleshooting some major EMC problems for a while so I decided to grace the project with a song. Here's my latest draft. Suggestions?

"The Sound Of Crosstalk"
(to the tune of The Sound Of Silence) Hello crosstalk, my old friend
I've come to fight with you again
Because a field line softly creeping
Left microstrip while I was testing
And the waveform I was sending through my board
Still remains... it is the sound of crosstalk

This is how you're supposed to simulate a circuit with a resistor in it, right?

Device is a R20L125 rod resistor from ResNet Microwave (electrotechnik.com/pdf/ROD.pdf). I'm interested in simulating the flatness of a probe using it as an attenuator.

Vendor doesn't publish S-params. This model is mostly based on guesswork as I don't have a lot of details from their datasheet on internal construction (e.g. metal layer thicknesses).

But as a first order estimate, I calculate 7-10 fF shunt capacitance depending on frequency.

I've had an HP LaserJet all-in-one printer in my home office for a couple of years now. I finally ran out of black toner and had to swap the cartridge out.

The box had this cool anti-counterfeiting seal on it, which changes appearance as you tilt it. Let's take a closer look! There's a barcode and QR code that seem to be printed using fairly ordinary black ink on paper, and then there's a special insert (the blue area) where Magic(tm) happens.

Let's look at the "toner" microprint area.

Open offer: If anyone sends me one of these (or any other similar audiophool products) I'll do a full signal and power integrity workup on it. And send it back after if you want.

I'd love to see how awful that "low noise" power rail really is.

https://twitter.com/murrzbow/status/1467552481748176904

Oh, and of course these geniuses are throwing a fancy TCXO on the board to get "low jitter" clocking.

... except the actual NVMe interface is clocked by the PCIe refclk. Which is spread spectrum modulated on most motherboards.

Sample of the green corrosion (no white stuff present) being sent off for EDS.

I expect to see lots of copper but curious what the other peaks will be. Chlorine seems plausible. Also, I really need to get a polarizer or something on this scope... the glare with shiny surfaces like this carbon tape is pretty extreme.

Many of my followers, or anyone who works with higher end @TeledyneLecroy oscilloscopes, are probably familiar with the PCF200 test fixture.

It's a small piece of low loss PCB with two CPWG thru lines, one with a .1" header and the other with a clip for solder-in probes tips. @TeledyneLecroy The intended use is de-skewing of different probes: you terminate one end of the fixture, drive a fast edge into the other end, then place each probe at the same point on the fixture and adjust skew until you see the edge at the same point on the scope display.

AKL-PT5 v0.3 is here - major improvements from the previous iteration, and also discovered some limitations of my test setup. I'm going to need to build better fixturing for characterizing future stuff.

Here it is soldered to one of my CPWG thru-line fixtures. First off, the PCF200 test fixture I had been using for solderless testing seems to be a limiting factor in performance. More loss and worse ripples.

Red = probe clipped to PCF200
Blue = same probe soldered to this fixture

No de-embed on either.

Pushing resolution limits of the M80 by cranking zoom up to max and then cropping down a camera photo.

Some of the smaller features like scratches in the embedding resin and the glass fibers are probably in the single digit μm range. This is absolutely not what I bought the scope for, but it really shows off the capabilities of the optics.

There looks to be a tiny bit of colored halo on the bright copper areas. This is the standard achromatic objective, so not surprising.

Thanks to an extremely generous donation, we're one step closer to a high performance open hardware oscilloscope!

The FPGA for the prototype has been on backorder for a while. Still need to source frontend parts after more design work is done. Planned prototype specs: one channel, 500 MHz / 5 Gsps / 12 bits, 50 ohm SMA input, dual channel DDR3 SODIMM waveform memory.

Final system will be 4-8 channels in 1U, with actual channel count depending on PCB size.

Finally got a decent EM simulation on the SATA pairs done. Only took four days... seems I need to simplify it further still.

Let's take a look at the results. Here's insertion loss. S21 (red), is the left pair going through the layer change, S43 (blue) is the right pair with no layer change.

Looks like the layer change is introducing some kind of impedance mismatch.

Time for a bit of a thread on all of my various open hardware oscilloscope probe projects, where they are, and what the next steps are on each project. First off, the passive probes. All of these are resistive probes, so they have AKL-PT* part number prefixes (AntiKernel Labs, Passive, Transmission line).

Finally finished initial characterization of the @UCSC_OpenRAM OR1 test chips made on SKY130! Here's a thread of results.

I tweeted a bunch of preliminary results a while back but some of the numbers have changed due to methodology tweaks and refining of the test protocols. The OR1 test chip is an 8kbit (256 row x 32 bit) SRAM array with two bits of each byte bonded out to pins of a 64-pin QFN.

New year, new... fume hood filter?

Not how the saying usually goes, but that's how things go in my lab. This is a ductless hood with a stack of two filters, a doped carbon for organic vapor/acid gas followed by a HEPA to catch carbon particles, sanding debris, etc. Here's the service plenum with the access cover removed. I change the carbon filter annually and the HEPA only when I notice it's clogged enough to impair airflow.

This is pretty rare since I don't generate a lot of particles in the lab and the overall air quality is excellent.

UPDATE: Traced this to a timing issue in the FPGA design on the test harness, so these results are invalid.

Corrected results coming shortly...

https://twitter.com/azonenberg/status/1479957612556742656

Why does Amazon bother sending order confirmation / shipped emails anymore? There's no actionable information left in them.

All I know is "something shipped". I don't know *what* shipped, when it's arriving, the tracking number, etc. So all I do is delete them because it tells me nothing.

Also, I really wish there was a privacy setting to say "I don't use a mail provider that data-mines my inbox, please include full order details in the emails"

A week or so ago, @femtoduino asked me to help out with troubleshooting and reworking a prototype of the BOMU, a tiny USB-connected microcontroller dev board. It's a super dense six-layer board with multiple levels of blind vias.

Here's a bare board after removal of back mask. So far, there's two known problems with it.

1) A blind via from layer 2 to 6 collides with a trace on layer 3. This is a design bug that slipped through DRC somehow, and results in SWCLK being shorted to a power rail.

Preparing to apply shielding paint to the new rev AKL-AD3 enclosure. This time I'm trying electrical tape instead of Kapton tape as a masking material, we'll see if it helps with less bleed-through / overspray. It's a little hard to see in this view but the new design has 45 degree angled interior walls to provide a smooth transition between horizontal and vertical. This should provide better paint coverage and conductivity.

Continuing to play with the SSG5060X-V demo, testing the LFO. This is normally used as the source for analog modulation, but you can also output it directly via a front panel port which is handy.

Note that the SSG output level is in Vpp and the DMM only reads in Vrms. The LFO can also be used to produce DC signals, so you get a free DC reference/bias voltage generator.

The levels seem dead on, this test is 500 μV low. And some of that might be tolerance of the 50Ω terminator I have across the DMM.

So @lukego was asking about component storage and lab organization in another thread. Thought I'd show you guys how I did it. Suggestions on how to improve are welcome! All of this stuff lives inside a single large cabinet with bins mounted on internal rails.

I also use the same bins inside other cabinets and on shelves/workbenches for organization. Each in-progress project has one or more bins for dedicated supplies.

Just got the capacitor samples from @Applied_Ion. First problem: they're HUGE. Like almost half an inch across.

Doing a sagittal section of this in my normal embedding molds is going to be impossible, and there's no way it will fit on the microscope stage either. @Applied_Ion First attempt at gluing the undamaged cap to a random scrap PCB with Crystalbond 509 failed with a cracked top. Can't let that happen to the real specimen!