I am now a CDC dude, testing my async FIFO with PRBS to verify my design at any clock ratio, watching the full and empty signals clean on the logic analyzer, trying my circuit on a UL3S FPGA, and if you understand it, it is easy peacy, thanks to Clifford E. Cummings from Sunburst Design.

Straight from Compton. Behind the bars!

https://x.com/splinedrive/status/1964746937426723179

December 2022—the moment of joy when I, an idiot, wrote an SDRAM controller, and my custom RISC-V CPU was about to run the memory test... Then I discover that @NoManJourney made a video about my controller without even mentioning me :) —LMAO. BTW, I recently fixed a bug that is now corrected in my repo.

How do I start with logic design?

Hello everyone, I am currently processing my three years of experience. I want to document my learning progress in this thread whenever I feel like it. I want to give something back. I will briefly describe the topics I have tackled successively and provide links. Fortunately, I have been documenting my journey on platform X for the last three years, mostly through videos, as they show how things work. Photos are not very informative for me and I often don't understand them because they don't convey behavior. #logicDesign #fpga #verilog #asic #nand #nor #and #not #or #inv #gate #boolean #MHz #clock #logicDestroyer A short story. How it all began.

After a serious bike accident in 2019 at a bike park in Austria, which left me bedridden for half a year, I started tinkering with ATtiny85 and Arduino stuff. Such things had never really interested me because I always work with Linux SoCs at my job, and I considered these small devices to be just beginner's toys. I didn't understand this stuff at all. I had bought an Arduino robot for my young son, and I started modifying the program code using the Arduino IDE. I began buying almost everything from eBay because I couldn't understand why such things were so darn cheap: GPS, sensors of all kinds, so much stuff. Much of it lies around here and has not been touched to this day. But really, it was all for my son.

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So folks, let me introduce the KianV RISC-V SV32 RV32IMA Real MMU Linux SoC. I've hacked a bootloader that boots from an SD card, and the design worked without any problems right away. I'm both surprised and shocked, it took less than a month, and we can boot LINUX on the FPGA. Just for fun, I tried my design on the FPGA, unoptimized, without TLB, without caches. It runs great. I am in love. Everything from scratch. Self-reliance is key for a hacker.

Okay, I have created a new code base for my RISC-V Linux SoC: generic UARTs, default 2, and SD card support. The SPI driver was blocking, which has been fixed, and the kernel driver has been adjusted accordingly. Future developments will be exclusively for ULX3S. 70 MHz 😭💢💯 I don't know if that's good. But for an RV32IMA processor with interrupt logic, privilege modes, flash controller, generic SPI controller usable for SD card/NOR flash/SPI dev, SDRAM controller, and generic UART (in this case configured for 2), it's around 6800 LUT4.

In this thread, I will try to teach you about a RISC-V processor, piece by piece! You can take a look at the image that depicts the instructions and registers of an RV32I (simpelst) and ask questions before we gradually delve into the design. #riscv #twitterSchool 1 Oh, I forgot about the registers! Registers are memory in the CPU. They range from x0 to x31. A register has 32 bits in RV32I. The content of x0 is always zero, but we'll get to that later. The registers also have other names (on the right). But let's ignore that for now. 2