Patent: Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas - GLOBALFOUNDRIES
In IEDM 2024, Intel researchers will presented a unique gate oxide atomic layer deposition process a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors.
From the proposed method it was achieved record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors.
Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device.
In patent writing it is good practice to avoid unnecessarily extending the explanation of likely application of the invention and to focus on explaining the innovation that is desired to be patented. In the case of the cited patent, this fact occurs.
The patent does not clarify a priori where the innovation will be applied, suggesting that the processor in question can be a CPU, a GPU, or even a combination of both, focusing exclusively on the details of the invention.
About Intel Ocean Cove: Since the beginning of 2018, I had been following the work of the Hillsboro team, looking forward to have access to the first patent of the disruptive new architecture that was being developed... And in 2019, this patent was finally published.
Upon analyzing it, I was absolutely shocked by what I saw and was certain that this patent would never be granted in the state in which it was presented. However, yesterday I received notification that this patent had been granted.
I could make a long article to show the details about this architecture, but it is preferable to show throughout this thread why this patent was kept in my Pandora's box for so long.
Things I was doing while I was recovering from ear infection: Studying the proposed 3D SRAM structure which Intel will use in its future processors together with its 20A node...
This is the 3D nanoribbon-based 6T SRAM cell proposal
This is the 3D nanoribbon-based 8T SRAM cell proposal
By reverse-engineering the ip-stride prefetcher in modern intel processors, the researchers have successfully developed three variants of AfterImage to leak control flow information across code regions, processes and the user-kernel boundary.
This new side-channel attack does not rely on changes to the control flow graph and does not rely on branch-speculative execution, defeating many recent defences against transient side-channels.