Also, I am looking for verilog (or VHDL) dev willing to help me on the project. I think I really need support.
Please share the message, it is important.
I plan to share income from the Patreon, but only after milestones have been achieved (most of the people who helped me before did not deliver a single line of code after weeks (and in the end), I won't share in advance...)
I am looking for people interested in :
CPU:
- CPU integration (or remake)
- Integr. of GTE module into CPU.
- Integr. of Cache/Scratchpad into CPU.
Other:
- DMA / bus impl./ BIOS
- DDR debug
- CD Rom impl. (SW 90%)
- Dbug on FPGA board
- Integr. of other modules
Recu ce matin un colis pour mon fils de la part de mon beau pere. Valeur declaree 22500 yen (176 euros). J'ai du payer un cheque de 69 euros sinon @ChronopostFr repartait avec notre colis.
39% de taxe vs 0% que j'aurais du paye, ca ne vous dit rien ?
Dessus du colis : declaree en GIFT bien sur.
J'ai envoye un mail a Chronopost pour voir a ce que mon cheque ne soit pas encaisse. Mais vu que on vis dans un monde ou il faut deballer le linge en public pour que les choses avance. Voila, je met ma pierre a l'edifice.
Oui, je suis bien enerve de payer 70 euro pour un polo.
While I understand the need for mod and kits to be produced in small quantities, I don't understand the concept of limited batch when they sell in just a few minutes.
I hope the people making those will at least continue to produce those kits, and at some point 1/n
saturate the customer need and that anybody can get one.
The fiasco of the Analogue Pocket was a good example of such policy.
I got interested in the ODE things in the last few weeks only, and looked at today's sales of the GC one.
While I did not plan to buy any, 2/n
800 units sold in 4 minutes. Yes. 4 minutes.
Why not do pre-order with batch based on user quantities ?
Or do preorder period (like start at this date and stop at this date) and then produce those batches...
I am glad those projects exist, and they represent a lot of hard work.
PSX on FPGA, update #17 :
Now 95% done. RTPS / RTPT pass Amidog's test suite.
Remains :
- Only MVMVA instruction. (its two variants)
- Slow down instructions that takes less cycle than original timing.
- Faster DPCT (17 cycle instead of 18).
Computer also need to define data structure AND algorithm.
"Hi, I want a link list of name and price".
Ok, can the list be empty ? Do you want fast parsing, fast insertion ? Computer should even be able to refactor and switch to different data structure based on code run.
Same with algorithm :
- Sure but what happen when data set is empty ?
- What happen in this case ?
- At that step, we overflow, what do you want to do ?
Computer could generate code from natural semantic descriptions, but each ambiguities leading to multiple specs...