Discover and read the best of Twitter Threads about #fpga

Most recents (16)

#Highlights2021 for me: our #survey on efficient processing of #sparse and compressed tensors of #ML/#DNN models on #hardware accelerators published in @ProceedingsIEEE.
Paper: dx.doi.org/10.1109/JPROC.…
arXiv: arxiv.org/abs/2007.00864
RT/sharing appreciated. 🧵
Context: Tensors of ML/DNN are compressed by leveraging #sparsity, #quantization, shape reduction. We summarize several such sources of sparsity & compression (§3). Sparsity is induced in structure while pruning & it is unstructured inherently for various applications or sources. Various sources induce stru...Common structures of sparsi...
Likewise, leveraging value similarity or approximate operations could yield irregularity in processing. Also, techniques for size-reduction make tensors asymmetric-shaped. Hence, special mechanisms can be required for efficient processing of sparse and irregular computations.
Read 12 tweets
This December, enjoy 24 days of tasty #FPGA treats.
Follow @WillFlux to open them all. 🎁 FPGA Advent Calendar 2021 p...
💥Day 1: Doom iCEBreaker Edition

An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.

Watch:
Source: github.com/smunaut/doom_r… 1993 Doom title screen over...System block diagram showin...
@1bitsquared ⛵️Day 2: VexRiscv FPU

I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.

Source: github.com/SpinalHDL/VexR… VexRiscv FPU design showing...
Read 25 tweets
How much DooM can fit in a USB port? Quite a bit it turns out! A minuscule #Fomu #fpga board hosts my hardware/software re-implementation of the DooM render loop in the confines of a USB port (uses ~4200 LUTs and < 128 kB of internal RAM). (1/n)
This is a tiny piece of DooM in a 2.1x2.7 mm #fpga. That is pretty small! (can you see it below on the #Fomu board? you might have to zoom ...).

I created within a #riscv computer with specialized texturing and column drawing hardware. Designed to render DooM 1994 levels! (2/n)
The OLED screen is connected to the #Fomu through jumper wires soldered on the pads (a trick inspired by @brunolevy01 Fomu vga mod). (3/n)
Read 17 tweets
Please welcome a new addition to my collection of cheap #FPGA boards from eBay. This one is a PCIe variant of Pikes Peak accelerator from Microsoft. (1/8) Image
I have previously explored the Open CloudServer variant, in a special form factor and with a special motherboard connector. A longer description is available as a series of blog posts on my website: j-marjanovic.io (2/8)
USB cable contains the same chip as the previous board, and OpenOCD is able to detect the FPGA. It also reports the same part number as on the OCS variant - this is a really good sign. (3/8) Image
Read 8 tweets
PSX on FPGA, update #23:
Timer, Joystick and other things.

patreon.com/posts/41907082

#fpga #psx #MiSTerFPGA

Also, I am looking for verilog (or VHDL) dev willing to help me on the project. I think I really need support.
Please share the message, it is important.
I plan to share income from the Patreon, but only after milestones have been achieved (most of the people who helped me before did not deliver a single line of code after weeks (and in the end), I won't share in advance...)
I am looking for people interested in :
CPU:
- CPU integration (or remake)
- Integr. of GTE module into CPU.
- Integr. of Cache/Scratchpad into CPU.

Other:
- DMA / bus impl./ BIOS
- DDR debug
- CD Rom impl. (SW 90%)
- Dbug on FPGA board
- Integr. of other modules

PSX need YOU !
Read 4 tweets
PSX on FPGA, update #16 :

GTE hardware implementation 86% complete.
Registers 100%, microcode 86%, data path and other mostly complete.

patreon.com/posts/39562211

#fpga #psx #MiSTerFPGA
PSX on FPGA, update #17 :
Now 95% done. RTPS / RTPT pass Amidog's test suite.

Remains :
- Only MVMVA instruction. (its two variants)
- Slow down instructions that takes less cycle than original timing.
- Faster DPCT (17 cycle instead of 18).
Same content but posted on Patreon :
patreon.com/posts/update-1…

#fpga #psx #MiSTerFPGA
Read 4 tweets
Hey everyone! I did a thing today. #FPGA Recall that tweet by @fpga_dave? Well, that day I ended up sending a message to @LatticeSemi via their web form. I didn't actually expect a reply. However, they DID.
1/
And so I replied to that email, with a longer response expressing some of my thoughts of the state of the relationship with the open source community and an invitation to discuss in more detail. I didn't expect a reply there, either. But they DID.
2/
@LatticeSemi invited me to a conference call with 3 of their senior execs. I accepted! As I don't think I'm qualified to be the spokesperson for the open source community, I arranged for @esden to join me on the call. He was of course his usual charismatic & informative self
3/
Read 16 tweets
--- PSX on FPGA ---
Update #11 : New post about PSX FPGA (Visible to everybody)
I think you'll like it.

patreon.com/posts/37038491

Stay safe.

Please like / RT for project awareness as usual.
#fpga #psx #MiSTerFPGA
Seems I found my next bug !
(Sending GPU command from Avocado PSX emulator feeding my GPU)
Trying a GIF... :-)
Read 5 tweets
The DooM-chip! It will run E1M1 till the end of times (or till power runs out, whichever comes first).
Algorithm is burned into wires, LUTs and flip-flops on an #FPGA: no CPU, no opcodes, no instruction counter.
Running on Altera CycloneV + SDRAM. (1/n)
Everything is described in a language I am working on: SDRAM controller, divider, BSP traversal, texture unit, etc.
Main renderer (w/o data) is 666 lines of code (!).
A great test case, made quite a few improvements, fixed some issues, learned a lot on CycloneV + Quartus.
(2/n)
Rendering uses the original BSP tree (of course!) but is modified to better fit a hardware implementation ; columns are raycast and drawn immediately front-to-back, stopping as soon as fully filled.
(3/n)

fabiensanglard.net/doomIphone/doo…
Read 9 tweets
Wolfenstein 3D render loop in pure hardware! No CPU, no instruction pointer, no opcodes, only wires and flip-flops. Here runs on a Mojo V3 board (Xilinx Spartan 6) + SDRAM. Reading @fabynou black books while learning about #FPGA could only lead to this ;-)
(1/n)
Implemented from scratch using my language, from the SDRAM double-framebuffer to the Wolf3D DDA algorithm (and this is the original one; fixed point, DDA loop with only adds and shifts, tangent table!). 320x200, 256 18-bits colors palette and VGA output -- old school!
(2/n)
DDA algorithm heavily building on the original @ID_AA_Carmack AsmRefresh impl.:
github.com/id-Software/wo…

Fascinating to look back into it! Love these runtime patches ;-)

mov [BYTE cs:horizop],OP_JLE ; patch a jle in

(can't do on FPGAs ... unless reconfig at runtime ...??)
(3/n)
Read 4 tweets
Happy 25th birthday to the Playstation 1.

And happy birth to my patreon for the PSX FPGA Project :
patreon.com/laxer3a

Here is the appetizer...
#misterfpga #playstation1 #fpga
This is a simulation of the hardware GPU, each frame is 50 clock cycle. See my patreon post ;-)
Please RT like crazy :D :D :D
Read 4 tweets
A BIG SUCCESS!

I've just found the right combination of #DisplayPort Transfer Unit (TU, aka "Packet Size") and Pixels per TU to allow standard 720p pixel clock down a single DP lane (and #FullHD down two lanes) - 40 bytes, with 11 pixel.

Life has become easy....
Sorry, just having a major #nerdgasm here.

I've been playing with #FPGA #DisplayPort and for a few years, and I have metaphorically found the keys to easy implementation of standard 720p & 1080p video while pulling weeds in the garden.
Now I have a #FirstNerdProblem... work on this tonight or watch the @spacex launch?
Read 4 tweets
Taking a couple of days off to see my pinball fanatic buddy Stuart in the UK. I want to make a pinball #fpga mashup! We're going to try and intercept ram writes and figure out when the high score is broken!
On the train to the airport I will test my verilog model of the SRAM against the real thing and see if I can read and write to it.
Installed the SRAM adapter board and then machine wouldn't start! Fairly terrifying! After an hour of debugging traced to a blown fuse and dodgy socket... Phew! 😌
Read 15 tweets
my next #fpga project as suggested by @ico_TC: Fourier analysis of fast ADC with results shown on a VGA monitor. This is such a cool video to understand what Fourier analysis is:
and this is a great paper on implementing the FFT in hardware - didn't think it was going to be so tricky! web.mit.edu/6.111/www/f201…
OK, @ebrombaugh gave me a tip on the sliding DFT comm.toronto.edu/~dimitris/ece4…
which looks a lot simpler to implement on an #FPGA. I've written the algo in python to test against the numpy FFT. github.com/mattvenn/fpga-…
Read 14 tweets
When activate IRQ on Zedboard with custom IRQ => Data Abort IRQ with Xilinx network code... Nice !!! #FPGA #HateShitLikeThat
Shit like that EVERYDAY !!! It gets REALLY TIRING !!!
So my code is fucked. IRQ broken.
Read 3 tweets
Breaking news !!!
Now custom chipset tested with sample asset & loader...
#fpga #2D #demoscene #oldschool
Still bug decoded in comments... Image
- Image not stable... Was stable before. WTF.
- DDR clock to verify (pixel and not bus ?!)
- Priority of 2D over CPU...
Time to sleep... near 3 AM. Science says that brain will start to eat itself if no sleep...
Read 3 tweets

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