Also, I am looking for verilog (or VHDL) dev willing to help me on the project. I think I really need support.
Please share the message, it is important.
I plan to share income from the Patreon, but only after milestones have been achieved (most of the people who helped me before did not deliver a single line of code after weeks (and in the end), I won't share in advance...)
Recu ce matin un colis pour mon fils de la part de mon beau pere. Valeur declaree 22500 yen (176 euros). J'ai du payer un cheque de 69 euros sinon @ChronopostFr repartait avec notre colis.
39% de taxe vs 0% que j'aurais du paye, ca ne vous dit rien ?
Dessus du colis : declaree en GIFT bien sur.
Sep 10, 2020 • 7 tweets • 2 min read
While I understand the need for mod and kits to be produced in small quantities, I don't understand the concept of limited batch when they sell in just a few minutes.
I hope the people making those will at least continue to produce those kits, and at some point 1/n
saturate the customer need and that anybody can get one.
The fiasco of the Analogue Pocket was a good example of such policy.
I got interested in the ODE things in the last few weeks only, and looked at today's sales of the GC one.
While I did not plan to buy any, 2/n
Jul 21, 2020 • 4 tweets • 3 min read
PSX on FPGA, update #16 :
GTE hardware implementation 86% complete.
Registers 100%, microcode 86%, data path and other mostly complete.
#fpga#psx#MiSTerFPGA
PSX on FPGA, update #17 :
Now 95% done. RTPS / RTPT pass Amidog's test suite.
Remains :
- Only MVMVA instruction. (its two variants)
- Slow down instructions that takes less cycle than original timing.
- Faster DPCT (17 cycle instead of 18).
Jul 4, 2020 • 9 tweets • 2 min read
As long as the computer is not asking back the intent for any ambiguous definition, automatic code generation from natural languages are doomed.
Computer also need to define data structure AND algorithm.
"Hi, I want a link list of name and price".
Ok, can the list be empty ? Do you want fast parsing, fast insertion ? Computer should even be able to refactor and switch to different data structure based on code run.
May 12, 2020 • 5 tweets • 2 min read
--- PSX on FPGA ---
Update #11 : New post about PSX FPGA (Visible to everybody)
I think you'll like it.
Please like / RT for project awareness as usual. #fpga#psx#MiSTerFPGA
Seems I found my next bug !
(Sending GPU command from Avocado PSX emulator feeding my GPU)
Dec 10, 2019 • 5 tweets • 1 min read
Little test with Twitter.
The image is 6000x6000 pixels.
This is the design of my chip as of tonight. Not complete still... You can see all the logic gates and all the things that goes in.
Some stuff is not well shown : a single adder or multiplier is also shown as a single box.
Dec 3, 2019 • 4 tweets • 2 min read
Happy 25th birthday to the Playstation 1.
And happy birth to my patreon for the PSX FPGA Project : patreon.com/laxer3a
Here is the appetizer... #misterfpga#playstation1#fpga
This is a simulation of the hardware GPU, each frame is 50 clock cycle. See my patreon post ;-)
Nov 28, 2019 • 9 tweets • 3 min read
PSX has a thing like a mask bit in the buffer you render to.
It is like a stencil buffer of 1 bit in OpenGL. Except that the stencil write value can be decided by the texture.
In the PSX, it means that you need to READ the buffer before writing to it... wasting bandwidth,not...
It seems obvious from the benchmark (made by Avocado's emu author) that it is using a trick somehow. Most likely the VRAM / SGRAM.
What I did is to implement a STENCIL CACHE (ST$) in FPGA.
The idea is to cache the status of all the bit 15 for all the VRAM for all 16 bit values.
Nov 23, 2019 • 7 tweets • 2 min read
I did not tweet much about my project.
I have been spending roughly 7+ month free time on making the PSX in FPGA. (All chips except CPU)
Today, I finally did plug all the parts of my PSX's GPU implementation together.
The goal is to work at 33.8 Mhz like the original.
My design is most likely completely different internally.
I have a double pixel pipeline (should be able to push 2 pix / clk) even textured.
Arch. support for burst handled but for now only a fake memory bus for verilator debug.
Here is my understanding (just from docs/talk) :
In the case of NVidia VRS, we saves on shader compute operations (and tex read).
But do not save on target buffer bandwidth read/write. (= even if we compute 1 pixel, we write 4 pixels to the target buffer)
On mobile, Apple probably decided that bandwidth was MORE critical...
Changed mostly NOTHING (see previous post). Rebuild. Timing Noise gone 95%.
Hummm... Overly arrogant about 100Mhz clock + 55 Mhz pixel clock
Note : glitch inside image are most likely a D-Cache issue with CPU write. Would not worry much.
Still have wobbling...
