On the threat model of @Ledger Nano and its ETH app when using DeFi.

Thread
[1/n] Image
Ledger Nano devices threat model is quite simple and could be summarized as follows:

1. Confidentiality of keys
2. Secure use with user consent
3. Genuineness check
4. Users' privacy

[2/n]
donjon.ledger.com/threat-model/
To ensure user consent, the device implements a Trusted Display. Only the info displayed on the device's screen can be trusted.

When you want to make an ETH transaction, you have to verify amount, recipient and fees on the device

[3/n] Image
When it comes to smartcontract interaction, it becomes more tricky. It's not possible to parse smartcontracts calls and make them human readable in a generic and trusted way.

In this situation, there are 2 cases:

[4/n]
Case 1 - The smartcontract call is supported and the device is able to display all the relevant data to the user.

This is the case for ERC20 transfer, Coumpound or ETH2 contract deposit.

[5/n]
ledger.com/blog/lend-dire…

ledger.com/blog/ledger-is…
Case 2 - The smartcontract is NOT supported. To avoid users having locked funds, it's still possible to blind-sign (no human readable data) the interaction.

In such a case, we're out of the Nano threat model, the security is reduced to any wallet without Trusted Display.

[6/n]
Blind signing is not secure, that's why we implemented a Trusted Display at the first place.

It's worth noting Ledger Live never asks for blind signing. Some 3rd party integration, like metamask or WalletConnect can ask for blind signing when the contract is not supported

[7/n]
For the future, we're working on a plugin mechanism for ETH app allowing easier smartcontract interaction implementation. We're also thinking about a better UX for blind-signing. It will be announced soon. Stay tuned.

[8/n]

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More from @P3b7_

12 Nov 20
Thread #PLATYPUS

PLATYPUS is a novel side-channel attack targeting Intel x86 CPU (including AES-NI, SGX).
> platypusattack.com

I'm not surprised that we discover new attacks on Intel CPU, while I'm very surprised this attack has just been discovered now.

(1/n)
PLATYPUS is a Side Channel Attack allowing to _remotely_ extract secrets from Intel CPU incl. SGX enclave and AES-NI.
It uses the unprivileged access to RAPL (Running Average Power Limit) interface to get an internal measurement of the power consumption of the chip.

(2/n)
From an attacker PoV, this interface is great since it's unpriviledged and can be accessed remotely.

On the other side, it's quite low resolution, you can only get samples at 20kHz. This later limitation is overcome by several of techniques (cf paper).

(3/n)
Read 10 tweets
29 May 20
I've read several misconceptions about Common Criteria certifications. Typically:
- "Components producers pay for certification"
- "Certifications test only against a known set of predefined scenarios"
- "Certifications are not a replacement for independant review"

Thread👇
(2/n)
In a Common Criteria Certification process (for a circuit). There are 4 actors:
1. The sponsor (SP)
2. The chip manufacturer (CM)
3. The 3rd party evaluation lab (lab)
4. The Certification body (CB)
(3/n)
Often SP and CM is the same entity, but not always.

The lab is an independant security eval entity accredited by the CB. There's no commercial relationship between lab and the CB. Regularly, the CB audits the lab to verify its skills.

Labs can lose their accreditation.
Read 10 tweets

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