Looking at the two new Sunway papers up for the Gordon Bell. None of them are Exaflop on FP64, for clarification.
The Quantum paper showcases 1.2EF using FP32, 4.4EF using mixed, on 41.9M cores. No FP64.
The nuclear paper showcases 298PF using FP64 on 40.4M cores.
The Quantum paper showcases 1.2EF using FP32, 4.4EF using mixed, on 41.9M cores. No FP64.
The nuclear paper showcases 298PF using FP64 on 40.4M cores.
It's worth noting that the definition of 'core' is being stretched here. Each chip is listed as having 390 cores - that's 6 groups of (8x8 compute elements + 1 management element). The management element has 512-bit SIMD, unclear what the compute elements can do with vectors
I suspect the management element also acts as the front-end for the compute elements in compute element-only mode.
So what we're really counting here is just execution ports that aren't AGUs or L/S
So what we're really counting here is just execution ports that aren't AGUs or L/S
Each 390-core chip thus has 6 groups of 65 'cores', but also each group has a 128-bit DDR4-3200 controller, good for 51.2 GB/s, or dual channel DDR4. In total, that's 12 64-bit channels of DDR4 for 307.2 GB/s. Paper says 96 GB per chip, so 8 GB of DRAM per channel.
But it means each chip has 12 memory slots, and there are 107520 of these chips in the Sunway system. Would be interesting if they're able to get 2 chips or 4 chips per 1U with that many memory channels. It is only 1 DPC though.
Will cite this tweet, which suggests the Sunway system can do FP64 Exaflop.
Sounds like the CPU isn't final?
But 35 MW across 107520 chips means provisioning 326 W per chip. With 70% overhead, each chip is about 190W then? So air cooled is possible.
Sounds like the CPU isn't final?
But 35 MW across 107520 chips means provisioning 326 W per chip. With 70% overhead, each chip is about 190W then? So air cooled is possible.
https://twitter.com/HPC_Guru/status/1460269583240085509
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