Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & ChipFlow founder member.
@matthewvenn@chaos.social
Jul 9, 2024 • 5 tweets • 2 min read
Look at this cool interdigitated transistor! This is a way of building chonkier transistors by putting them in parallel. This one has 3 gates, 2 sources and 2 drains and can work at 5v.
I’m using it as part of a mixed signal ASIC project that will digitally synthesise a sine wave and then output the signal at 3.3v.
Taking a couple of days off to see my pinball fanatic buddy Stuart in the UK. I want to make a pinball #fpga mashup! We're going to try and intercept ram writes and figure out when the high score is broken!
On the train to the airport I will test my verilog model of the SRAM against the real thing and see if I can read and write to it.
Jun 3, 2018 • 14 tweets • 7 min read
my next #fpga project as suggested by @ico_TC: Fourier analysis of fast ADC with results shown on a VGA monitor. This is such a cool video to understand what Fourier analysis is:
and this is a great paper on implementing the FFT in hardware - didn't think it was going to be so tricky! web.mit.edu/6.111/www/f201…