The trend for graphics architecture is reduced ALUs per SM/CU, as it is difficult to keep utilization high. Shared registers & cache subsystem, and instruction fetch, decode, and warp schedulers all have to be expanded to utilize the extra ALUs.
https://twitter.com/3DCenter_org/status/1402492149875286023
At which point it's more advantageous to just expand number of SM/CUs. Kepler -> Maxwell -> Turing etc went from higher ALUs per SM to 64. Its only Ampere where FP32 is doubled, but its really a datacenter compute focused design.
The easy part of 3D rendering is splitting up the scene into small chunks, can be 8, 16, 32, 64 ^2 pixel groups, where the CU/SM handles them in parallel. Its not advantageous to have very wide CU/SM (utilization), which are more useful for some compute workloads.
Though there are increasingly more compute shaders that can scale better with wider CUs, especially with Async Compute, you will still need the underlying subsystems capable of supporting that many ALUs concurrently, and that eats die area & power.
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