Continuing to play with the SSG5060X-V demo, testing the LFO. This is normally used as the source for analog modulation, but you can also output it directly via a front panel port which is handy.

Note that the SSG output level is in Vpp and the DMM only reads in Vrms.
The LFO can also be used to produce DC signals, so you get a free DC reference/bias voltage generator.

The levels seem dead on, this test is 500 μV low. And some of that might be tolerance of the 50Ω terminator I have across the DMM.
At 1.0V DC output, still looking very good. <1 mV off nominal.
Frequency accuracy of the LFO is excellent as well. I suspect that my multimeter is actually the limiting actor in this measurement, not the SSG.
In case anybody is wondering why they make SMA-to-banana-jack adapters, this is a perfect example of why!
For the next test, I'm going to try to measure leakage between the RF and LF ports.

The LFO is outputting a 100 kHz sinewave at -40 dBm. I'm viewing it with my PicoScope 6824E to take advantage of the 12-bit ADC for improved sensitivity.

RF port is driving +10 dBm into 50Ω load
So we have a super weak LFO with an interferer 50 dB stronger in close proximity within the SSG.

Here's the LFO output spectrum with a 1 MHz +10 dBm RF signal on and off. Can you tell which is which? I can't. Excellent RF-LF isolation, any leakage is below the noise floor.
Maybe coupling is stronger at higher frequencies? Here's a 101 MHz test (there was a weak spur at 100 MHz present even with RF off - maybe leakage inside the PicoScope - that I wanted to avoid).

Again, no measurable leakage. Very happy.
When I say "weak spur" I mean like -110 dBm.

It might actually be coming from the SSG but not the RF path? Seems to be present on the RF input (channel A) but weaker to absent on the floating input (F).

Not something I'm bothered by in the slightest, though.

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More from @azonenberg

5 Oct
Preparing to apply shielding paint to the new rev AKL-AD3 enclosure. This time I'm trying electrical tape instead of Kapton tape as a masking material, we'll see if it helps with less bleed-through / overspray. Image
It's a little hard to see in this view but the new design has 45 degree angled interior walls to provide a smooth transition between horizontal and vertical. This should provide better paint coverage and conductivity. Image
I painted the last rev in the fume hood to keep the lab from smelling like solvents, but noticed a huge spike on the particle counter after.

Seems like the solids in the shield paint were getting airborne and making it through the carbon filter in the hood. So I fixed that. ImageImage
Read 4 tweets
9 Aug 20
So @lukego was asking about component storage and lab organization in another thread. Thought I'd show you guys how I did it. Suggestions on how to improve are welcome!
All of this stuff lives inside a single large cabinet with bins mounted on internal rails.

I also use the same bins inside other cabinets and on shelves/workbenches for organization. Each in-progress project has one or more bins for dedicated supplies.
These bins currently sit on a shelf built into the wall, but I eventually plan on adding a wall-mounted rail to hang them on so I don't have to move the ones on top to get to the bottom of the stack.
Read 5 tweets
15 Oct 19
Just got the capacitor samples from @Applied_Ion. First problem: they're HUGE. Like almost half an inch across.

Doing a sagittal section of this in my normal embedding molds is going to be impossible, and there's no way it will fit on the microscope stage either.
@Applied_Ion First attempt at gluing the undamaged cap to a random scrap PCB with Crystalbond 509 failed with a cracked top. Can't let that happen to the real specimen!
@Applied_Ion Crystalbond all over the top didn't help either. The heat of sawing just turned it into a goopy mess of capacitor dust and adhesive.
Read 13 tweets
6 Jan 19
Having a really strange bug bringing up Ethernet on STARSHIPRAIDER. When I force the link speed on my switch to 10M, it links up and appears to be OK (although my MAC doesn't run in 10/100 mode yet so I can't actually test with TCP/IP traffic)
100M and 1G modes flap constantly and won't stay linked up. Suspecting signal integrity or power problem.

Tried swapping cables and switch ports already, no luck there.
Scope captures of the various 1000base-T test patterns look fine, as do eyes on 100baseTX transmit (I can't do CDR on 1000base-T yet). All power rails appear to be the correct voltages. Visually inspected all solder joints and touched up any questionable ones.
Read 7 tweets

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