No come on, please. Is this your blind spot? Really?
Sometimes you have to tell your CEO where their blind spots are.
'We're ahead of schedule to where I thought we'd be when I joined'
Only Intel can spread across all these
Executing on strategy - future of growth begins today.
> Today? Not... last month?
>The six business units are a good breakout. Does the Custom Compute for blockchain section become a 7th?
Quecca-scale.
What. The. WTF.
I'd write all the buzz words Pat is saying right now, but it's not needed.
Driving Moore's Law. Note the 'Transistors per package' metric.
1 trillion transistors per package by 2030.
@CerebrasSystems was doing that with wafer scale in 2020. Just some perspective here that some (well-funded) moonshots already exist.
PG: I helped create USB. My daughter plugs in a stick and says 'thank you papa'.
<silence in the room>
What was... that...?
Enabling open ecosystems
Geographically resilient supply chains
Based on this graph, USA never led?
USA CHIPS Act, EU CHIPS Act, Intel going after incentives
Why is Alder Lake is quotes, but none of the others are?
Pat says he wants one of the Mobileye cars. He's the CEO, why can't he have one?
Five nodes in 4 years.
'Doesn't it take 2 years per node?'
'Intel will catch up quickly'
That's because all node updates become new numbers, rather than a +
Manufacturing has almost 'an unlimited budget' to get Intel back on track
PG: Grove used to say 'we gave you an unlimited budget and you still overspent'
<silence>
Process Leadership is based on perf/watt. It's a very important distinction to remember
Meteor Lake hasn't taped out yet. Later this year.
First SRAM Wafers of 18A. GAA/RibbonFET test chips
PG's 'Simba' moment.
PG: If you weren't amazed by Ann's presentation this morning, you're not a geek.
huh... what? Really? What is this statement?
New megafab location in Europe coming
Intel creates growth engines for the industry
More software engineers at Intel than Pat was managing at VMWare, a software company.
...aaaaand there's the religious reference.
Intel's software is a differentiator
How much $ is Intel making from software today?
PG: The Best Team in the Industry
Did you hear that $TSM $NVDA $AMD Samsung
PG: 17k new employees in 2021. The Brain Drain is gone.
PG: We invented OKRs
what?
Intel revenue growth expectations
PG: None of the following assumptions are heroic
Arrow Lake name now confirmed
Alder Lake 12th Gen
Raptor Lake 13th Gen
Meteor Lake 14th Gen
Arrow Lake 15th Gen
Xeon updates. Granite Rapids, Sierra Forest
Sierra Forest is an all E-core version of Xeon for 2024
New platform every 2 years. New product every year.
Emerald Rapids will have increased core count, but feature compatible with Sapphire Rapids
Alder Lake leverages 'Hybrid' architecture
Pat then uses that as a point to mention that Xeon will do similar, but all P-core and all E-core. No Hybrid for Xeon
Intel 3 process node ?
PG: 2024 is an inflection point in competitiveness
Networking and Edge: NEX
PG: Shifting networking compute on dedicated silicon, leaving CPU free to do normal work
AXG Revenue in 2021 was $0.7B
AXG Revenue in 2022 will be >$1B
So 4m GPUs for 300m up to 1.3b (?). How much revenue per GPU?
PG: 'Business ain't fair'
PG: HPC has been niche for 40 years. Now is mainstream.
PG: Developer ecosystem is pumped
Falcon Shores. One CPU chiplet, two Xe chiplets. ? Or a central IO die with Xe GPU, and two CPU chiplets?
Automotive
IFS - Intel Foundry Services
Strong pipeline of customers
Already running 30+ different test chips in 2022
What's the scale on this revenue graph? Does is start at zero? So a 2x increase in revenue by 2026?
OK so 2x from current offering, unknown revenue from future node offerings
18A on IFS in 2H 2024.
Add in Tower, available today. Wait, doesn't it close in 12 months?
Tower adds $1.5b revenue to IFS today.
EPS accretive.
But GMs are sub 20%.
What annoys me about this is PG stating that IDM and IFS are always positive feedback loops. If it goes negative, then it speeds up that spiral
Intel going to run factories on nodes much longer, requires build out of new facilities.
PG doesn't mention that it means lots of demand. One of the biggest fears is that market does a downturn in demand. PG defends this, saying they can bring more in-house. That's not easy
For example, if that happened today, you can't simply build the TSMC N6 GPU on an Intel 7 process and expect the same result overnight. It's a 3-5 year process to shift products from fab to fab.
PG: Not all these need to hit
1.0 model
2.0 model with IFS
PG: Use customer pre-pays to create capital flexibility
...who is prepaying? I mean, without MDF incentives
Pat teasing that CapEx intensity will decrease later in the decade.
What makes me think that if he wants to succeed, he can't let his foot off the gas.
PG: How do you know we are executing? We'll give you proof points with products on market and our roadmaps, like Alder Lake and Intel 7.
Me: That's not an answer. Those were in the pipe before you joined. Words are still words, not execution.
Roadmaps
PG: Aim to double revenue and double Intel's multiple. A 4x of shareholder intel value.
So, $800b market cap?
Sandra Rivera @SandraLRivera to the stage, talking datacenter and AI
More Ice Lake Xeon CPUs shipped in December than AMD shipped all year.
Just don't ask about ASPs and GMs
Sapphire Rapids, coming 2H22
Demo
The demo seems to not going well, they're showing the wrong videos
Intel: AI in the Xeon, no need for an Accelerator
Also Intel: But we'll also sell you an accelerator.
Here's the Future Xeon Roadmap. I'm glad we're getting roadmaps
SR: Intel 3 using higher density, higher performance libraries.
Which is it? high density, or high performance? Usually it's a scale. This is still FinFET based EUV, not GAA.
Intel can leverage its enterprise portfolio. No other company can do all of this at once. As a result, Intel is pushing combo Intel solutions for market value
$40B silicon TAM in AI by 2026. Seems low? Depends what you include
Now explaining what SGX again. Is it SGX or TSX that's been talked about, implemented, disabled, implemented, etc
Michelle Johnston Holthaus to the stage @MJHolthaus EVP of CCG
@MJHolthaus Number of PCs per household is increasing
Jim Johnson, Interim GM of CCG to the stage
Client revenue growing - still grew when Apple left and Intel divested two technologies (5G and memory?)
This graph is somewhat misleading. Plot back to 2018 when PCs were at a historic low. Are we really expecting >360m units per year for the next 5 years?
Cloud Client Experiences - immersive experiences through virtualization
Lunar Lake to use external chiplets
This confirms the Lunar Lake name then as well
Note that with Meteor and Arrow Lake, Intel won't have performance per watt leadership according to this
ADL is ramping fast
Sneak peak of Raptor Lake, 8 Perf cores, 16 Efficiency Cores
I can get more cores with Xeon Phu, just sayin'
'Up to double digit'. So less than 10%
Why is the AI M.2 module 'specific' to Raptor Lake? If it's M.2, it can be on any system
The annual @ieee_isscc#ISSCC22 conference is coming up next month and the presentation list is now live. Here are some of the talks I'm really looking forward to.
Session 2 is all CPUs, hoping to see if Intel says more about PVC and SPR 1/x
2/ This one is a bit out of left field. Intel is going to talk about ultra-low-voltage Bitcoin ASICs. The DS1 in this talk means there's going to be a demo of it (perhaps more than simulation work?)
3/ @tenstorrent is going to talk more about Wormhole, it's 3rd generation big 700mm2+ chip. Uses GDDR6 and 16 x 100 GbE for scale out - you can connect as many chips together in a 2D array to create the AI training chip you need with predicable on-chip/off-chip latency
Looking at the two new Sunway papers up for the Gordon Bell. None of them are Exaflop on FP64, for clarification.
The Quantum paper showcases 1.2EF using FP32, 4.4EF using mixed, on 41.9M cores. No FP64.
The nuclear paper showcases 298PF using FP64 on 40.4M cores.
It's worth noting that the definition of 'core' is being stretched here. Each chip is listed as having 390 cores - that's 6 groups of (8x8 compute elements + 1 management element). The management element has 512-bit SIMD, unclear what the compute elements can do with vectors
I suspect the management element also acts as the front-end for the compute elements in compute element-only mode.
So what we're really counting here is just execution ports that aren't AGUs or L/S
The Intel Advanced Architecture Development Group (AADG) is responsible for creating the next leap in Microprocessor Design and the future of the x86 environment at Intel by helping to solve the ‘Innovator’s Dilemma’ when it comes to a new core design for Intel.
This dilemma can be simplified into finding the answers to questions like:
Now I've had some time for the @Intel announcements yesterday to sink in, here's my brain dump.
A number of analysts were quite reserved when @PGelsinger joined Intel, stating that no matter what he did, we wouldn't see it for years. I said straight away that Pat can steer the intent of the company as soon as he sat in the seat. Today is a clear message
That being said, Intel last week is still the same as Intel today. Saying stuff doesn't mean much unless Intel does pivot, and it will take a few years to enable that pivot, but there will be a strong undercurrent of things to come throughout, with a continuous focus on 2023
For what it's worth, Intel has been using Arm cores in its products for years. Some we know about, others we do not. Some Intel products contain solely Arm cores.
As for their own custom cores, Intel has had an Arm architecture license for around a decade, if not longer.
How much has Intel used that architecture licence? Golden question. Given that Arm's own cores go from the M0 for microcontrol, up to the X1 for performance, and R-series for real time, and lots in-between, it's hard to say.
A modern CPU has a lot of microcontrollers.
Just don't ask what secret sauce they already add for big customers.