💥Day 1: Doom iCEBreaker Edition
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
@1bitsquared ⛵️Day 2: VexRiscv FPU
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
@1bitsquared @SpinalHDL 🏎️Day 3: PAWS SoC
Want to create your own #RISCV SoC?
@robng15 shows you how. PAWS features dual-thread CPU, HDMI output, UART, PS/2, and reads software from SD card. Rob developed PAWS with @sylefeb Silice and @RadionaOrg ULX3S dev board.
Source: github.com/rob-ng15/PAWS
Want to create your own #RISCV SoC?
@robng15 shows you how. PAWS features dual-thread CPU, HDMI output, UART, PS/2, and reads software from SD card. Rob developed PAWS with @sylefeb Silice and @RadionaOrg ULX3S dev board.
Source: github.com/rob-ng15/PAWS
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg 🏔️Day 4: Tiny Terrain Renderer
Perhaps you'd rather build a world than an SoC? Silice creator @sylefeb has you covered with Tiny Terrain Renderer. Sylvain creates breathtaking voxel scenery with an iCE40 FPGA.
Source: github.com/sylefeb/Silice…
Perhaps you'd rather build a world than an SoC? Silice creator @sylefeb has you covered with Tiny Terrain Renderer. Sylvain creates breathtaking voxel scenery with an iCE40 FPGA.
Source: github.com/sylefeb/Silice…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg 🛰️Day 5: Life on Mars
Exploring another world? Don't forget to pack your #FPGA. @NASAPersevere landed on Mars in Feb, seeking evidence of former microbial life. Onboard are @XilinxInc Virtex-5QVs and XQR2V3000 FPGAs.
Story: origin.xilinx.com/about/blogs/xi…
NASA: nasa.gov/perseverance
Exploring another world? Don't forget to pack your #FPGA. @NASAPersevere landed on Mars in Feb, seeking evidence of former microbial life. Onboard are @XilinxInc Virtex-5QVs and XQR2V3000 FPGAs.
Story: origin.xilinx.com/about/blogs/xi…
NASA: nasa.gov/perseverance
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc 😺Day 6: YosysHQ Founded
No one has done more for open-source FPGA than @oe1cxw. This year, Yosys, nextpnr, SBY, and Project IceStorm found a safe new home at YosysHQ.
I can't wait to see what the YosysHQ team have in store for 2022.
YosysHQ Tools: yosyshq.com/open-source
No one has done more for open-source FPGA than @oe1cxw. This year, Yosys, nextpnr, SBY, and Project IceStorm found a safe new home at YosysHQ.
I can't wait to see what the YosysHQ team have in store for 2022.
YosysHQ Tools: yosyshq.com/open-source
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw 🚀Day 7: Verilator Sim
Hardware simulation can be slow and intimidating. Verilator converts Verilog into a fast C++ model. Throw in a dash of SDL and enjoy visual simulations at 60FPS.
Project F's most popular blog post of 2021 shows you how: projectf.io/posts/verilog-…
Hardware simulation can be slow and intimidating. Verilator converts Verilog into a fast C++ model. Throw in a dash of SDL and enjoy visual simulations at 60FPS.
Project F's most popular blog post of 2021 shows you how: projectf.io/posts/verilog-…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw 📶Day 8: Bluetooth Receiver
@newhouseb built a BLE receiver using nothing but an #FPGA and antenna! No ADC, AGC, filters, mixers, or amplifiers required. RF into SERDES port sampling at 5GHz.
Written in nMigen with @TrenzElectronic TE0714 board.
Source: github.com/newhouseb/oneb…
@newhouseb built a BLE receiver using nothing but an #FPGA and antenna! No ADC, AGC, filters, mixers, or amplifiers required. RF into SERDES port sampling at 5GHz.
Written in nMigen with @TrenzElectronic TE0714 board.
Source: github.com/newhouseb/oneb…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic 🏀Day 9: FPGA PCB Design
Want to make your own #FPGA dev board? @benjamincpu designs and builds 2 and 4-layer PCBs with #KiCad. Ben looks at handling multiple voltages, BGA soldering, and Pmod connectors.
Blog: benjamin.computer/posts/2021-08-…
Watch:
Want to make your own #FPGA dev board? @benjamincpu designs and builds 2 and 4-layer PCBs with #KiCad. Ben looks at handling multiple voltages, BGA soldering, and Pmod connectors.
Blog: benjamin.computer/posts/2021-08-…
Watch:
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu 🧱Day 10: FPGA Craft
@nickmqb built an HDL (Wyre) and implemented #Minecraft with it! Custom raytracing GPU, dynamic lighting, flash texture streaming, custom 16-bit CPU, N64 controller… and it all fits onto iCEBreaker. Talk about impressive.🤯
Source: github.com/nickmqb/fpga_c…
@nickmqb built an HDL (Wyre) and implemented #Minecraft with it! Custom raytracing GPU, dynamic lighting, flash texture streaming, custom 16-bit CPU, N64 controller… and it all fits onto iCEBreaker. Talk about impressive.🤯
Source: github.com/nickmqb/fpga_c…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb 🤏Day 11: 6000 Cores, 1 FPGA
Take 6000 SERV #RISCV cores from @OlofKindgren, a chunky VU37P #FPGA, a dash of engineering from @sylefeb, and et voila: a multiprocessor monster!
Synthesis took 35+ hours.
Source: github.com/olofk/serv
News: hackster.io/news/new-cores…
Take 6000 SERV #RISCV cores from @OlofKindgren, a chunky VU37P #FPGA, a dash of engineering from @sylefeb, and et voila: a multiprocessor monster!
Synthesis took 35+ hours.
Source: github.com/olofk/serv
News: hackster.io/news/new-cores…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren 🍲Day 12: RISC-V Bytes
You've got a #RISCV CPU on your FPGA. Now what?
Take a look at RISC-V Bytes from @hasheddan, which breaks down real programs to see how they work. Learn about ABI, registers, stack, instruction formats, debugging, and more.
Blog: danielmangum.com/categories/ris…
You've got a #RISCV CPU on your FPGA. Now what?
Take a look at RISC-V Bytes from @hasheddan, which breaks down real programs to see how they work. Learn about ABI, registers, stack, instruction formats, debugging, and more.
Blog: danielmangum.com/categories/ris…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan 🧑🍳Day 13: Yosys Cookbook
If you use Yosys, you owe it to yourself to read @ravenslofty's cookbook. Started in 2020 but updated in 2021, it includes recommendations for iCE40, ECP5, & Cyclone V. Lofty also explains the potent ABC9 option.
Source: github.com/Ravenslofty/yo…
If you use Yosys, you owe it to yourself to read @ravenslofty's cookbook. Started in 2020 but updated in 2021, it includes recommendations for iCE40, ECP5, & Cyclone V. Lofty also explains the potent ABC9 option.
Source: github.com/Ravenslofty/yo…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty 🚥Day 14: Colorlight ECP5 Board
Prolific #FPGA board detective @tom_verbeure explains how to get the Colorlight i5 board up and running. The i5 features ECP5 LFE5U-25F, SODIMM GPIO, two Ethernet transceivers, SDRAM, and HDMI.
Blog: tomverbeure.github.io/2021/01/22/The…
Prolific #FPGA board detective @tom_verbeure explains how to get the Colorlight i5 board up and running. The i5 features ECP5 LFE5U-25F, SODIMM GPIO, two Ethernet transceivers, SDRAM, and HDMI.
Blog: tomverbeure.github.io/2021/01/22/The…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure ⏪Day 15: A new VAX!
The first new VAX in 30 years? On a Spartan-3 #FPGA, no less! Read more from Anders Magnusson on the NetBSD VAX ML back in July: mail-index.netbsd.org/port-vax/2021/…
I've never used a VAX. Have you? Perhaps I will in 2022?
The first new VAX in 30 years? On a Spartan-3 #FPGA, no less! Read more from Anders Magnusson on the NetBSD VAX ML back in July: mail-index.netbsd.org/port-vax/2021/…
I've never used a VAX. Have you? Perhaps I will in 2022?
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure 📸Day 16: Camera Video Adapter
No digital video from your thermal camera? No problem. Take an ECP5 FPGA, LiteX, Serv RISC-V core, the design and soldering skills of @GregDavill, and you get the FLIR Boson Digital Video Adapter.
Blog: gregdavill.github.io/posts/boson-fr…
No digital video from your thermal camera? No problem. Take an ECP5 FPGA, LiteX, Serv RISC-V core, the design and soldering skills of @GregDavill, and you get the FLIR Boson Digital Video Adapter.
Blog: gregdavill.github.io/posts/boson-fr…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill 🔊Day 17: FPGA Audio Synth
up5k_osc is a #Eurorack-format digital oscillator created by @ebrombaugh. Eric's oscillator generates analogue synth waveforms with minimal timing jitter and aliasing. Open-source PCB designed in KiCad with iCE40 #FPGA.
Source: github.com/emeb/up5k_osc
up5k_osc is a #Eurorack-format digital oscillator created by @ebrombaugh. Eric's oscillator generates analogue synth waveforms with minimal timing jitter and aliasing. Open-source PCB designed in KiCad with iCE40 #FPGA.
Source: github.com/emeb/up5k_osc
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh 🎶Day 18: reDIP SID
reDIP SID is a drop-in replacement for the MOS 6581/8580 SID with an iCE40 #FPGA. icesid is a Verilog SID reimplementation that runs on reDIP SID.
» github.com/daglem/reDIP-S…
» github.com/bit-hack/icesid
SID is the iconic sound chip from the Commodore 64. #C64
reDIP SID is a drop-in replacement for the MOS 6581/8580 SID with an iCE40 #FPGA. icesid is a Verilog SID reimplementation that runs on reDIP SID.
» github.com/daglem/reDIP-S…
» github.com/bit-hack/icesid
SID is the iconic sound chip from the Commodore 64. #C64
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh 🧪Day 19: Speeding Up Science
FPGAs can be 'moulded' to accelerate applications ranging from genomic alignment to image processing to deep learning.
An #FPGA is basically "electronic mud", says @BrunoLevy01.
Read more in @Nature: nature.com/articles/d4158…
FPGAs can be 'moulded' to accelerate applications ranging from genomic alignment to image processing to deep learning.
An #FPGA is basically "electronic mud", says @BrunoLevy01.
Read more in @Nature: nature.com/articles/d4158…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh @BrunoLevy01 @Nature 🧑🏫Day 20: Bruno Levy's Learn FPGA
Looking to read from SPI Flash? Get your ULX3S dev board up and running? Understand RISC-V design?
Learn FPGA from @BrunoLevy01 is full of information and ideas for anyone curious about FPGAs: github.com/BrunoLevy/lear…
Looking to read from SPI Flash? Get your ULX3S dev board up and running? Understand RISC-V design?
Learn FPGA from @BrunoLevy01 is full of information and ideas for anyone curious about FPGAs: github.com/BrunoLevy/lear…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh @BrunoLevy01 @Nature 🌿Day 21: Amaranth HDL
Created by @whitequark, Amaranth (formerly nMigen) is a promising new open-source language for hardware development. Amaranth v0.3 was released this month.
Source: github.com/amaranth-lang/…
Docs: amaranth-lang.org/docs/amaranth/…
Created by @whitequark, Amaranth (formerly nMigen) is a promising new open-source language for hardware development. Amaranth v0.3 was released this month.
Source: github.com/amaranth-lang/…
Docs: amaranth-lang.org/docs/amaranth/…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh @BrunoLevy01 @Nature @whitequark 🧊Day 22: iCEBreaker Bitsy
@1bitsquared is working on a new open-source iCE40 #FPGA dev board: iCEBreaker Bitsy. Compared to the original iCEBreaker, Bitsy adds 8MiB Ram and #Teensy pinout compatibility. Look out for it in early 2022.
docs.icebreaker-fpga.org/hardware/bitsy/
@1bitsquared is working on a new open-source iCE40 #FPGA dev board: iCEBreaker Bitsy. Compared to the original iCEBreaker, Bitsy adds 8MiB Ram and #Teensy pinout compatibility. Look out for it in early 2022.
docs.icebreaker-fpga.org/hardware/bitsy/
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh @BrunoLevy01 @Nature @whitequark 💻Day 23: #Linux + #RISCV + #FPGA
Could an FPGA power your next laptop?
@mntmn has created an open computer down to the CPU gateware. Linux runs on MNT RKX7 SoM with Kintex-7 FPGA and @enjoy_digital LiteX-VexRiscv.
» SoM: source.mnt.re/reform/reform-…
» LiteX: github.com/litex-hub/linu…
Could an FPGA power your next laptop?
@mntmn has created an open computer down to the CPU gateware. Linux runs on MNT RKX7 SoM with Kintex-7 FPGA and @enjoy_digital LiteX-VexRiscv.
» SoM: source.mnt.re/reform/reform-…
» LiteX: github.com/litex-hub/linu…
@1bitsquared @SpinalHDL @robng15 @sylefeb @RadionaOrg @NASAPersevere @XilinxInc @oe1cxw @newhouseb @TrenzElectronic @benjamincpu @nickmqb @OlofKindgren @hasheddan @ravenslofty @tom_verbeure @GregDavill @ebrombaugh @BrunoLevy01 @Nature @whitequark @mntmn @enjoy_digital 🎄Day 24: Merry Christmas
2021 has been a gruelling year, but I hope you've found these 23 projects inspiring. If you had to choose one FPGA project to add, what would it be?
Now if you'll excuse me, I have some Lemmings to save on my Amiga. Stay safe and I'll see you in 2022.
2021 has been a gruelling year, but I hope you've found these 23 projects inspiring. If you had to choose one FPGA project to add, what would it be?
Now if you'll excuse me, I have some Lemmings to save on my Amiga. Stay safe and I'll see you in 2022.
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