M1 Ultra Image
cor Image
Die to die 'ultrafusion'

Users silicon interposer. Twice the density of anything in the industry.

10000 links, 2.5 TB/s
4x bandwdith of leading edge Image
114 billion transistors ImageImage
800 GB/s DRAM bandwidth, 128 GB of unified memory ImageImage
16 performance cores, 4 efficient cores Image
64-core GPU Image
Fun comparisons ImageImageImageImage
GPU comparisons ImageImage
Overall Image
@dylan522p any idea what silicon interposer is being used?
One of the big things with M1 Ultra is going to be that GPU with 800 GB/s of bandwidth. Assuming the GPUs on each die can work collectively on a single task.

Actually, that's really important - can the GPUs work on a single task together? or is it an Xe Link scenario?
800GB/s is also not the real story. A single core can barely access 200 GB/s, so it's a collective effort to use that bandwidth
Announcing Mac Studio
The small one is Mac Studio. There's also Mac Studio display. Image
Guessing on price, Mac Studio probably starts at $4k ? More?
Single aluminium extrusion -
3.7-inch by 7.7-inch by 7.7-inch

Double sided blower
Custom circular power supply
Low impedance heatsink
'Barely hear it' for most workloads ImageImageImageImage
4 x TB ports
10 GbE RJ45
2 x Type-A
HDMI
2 x TB4 / Type-C 10 Gbps on front
SDXC port
Supports high impedance
Supports 5 x 4K displays ImageImage
CPU Performance ImageImage
GPU Performance ImageImage
Exact benchmarks likely to be on the website later
More CPU ImageImageImage
More GPU ImageImage
128 GB unified memory for GPU.

This'll be good for ML
8 TB of 7.4 GB/s SSD performance

No way to add extra though except through TB4 ports ImageImage
The specifications seem great.

The problem is that to take these pictures and do this tweet stream, I'm using custom scripts I've written using software that has no Mac counterpart.
and FWIW, this looks like a system crashed during Johny's section Image
I don't know what this means Image
Final specifications Image
Studio Display time.

Tilt and Vesa require a different stand. to buy Image
600 nits
5K retina, 14.7 MP
10-bit native
27-inch
Nano-texture option to minimize glare ImageImage
Has A13 Bionic inside Image
Comes with 12MP camera
3 mic array
six speakers for spatial audio

looks like two fans as well?
Does the A13 do noise cancellation? ImageImageImage
3 x 10 Gbps USB-C
1 x TB port, 96W power from monitor

Really needs two TB ports for daisy chain ImageImageImage
Sustainability Image
Pairs with an Mac Image
Spot the socket Image
as @bmastenbrook said, if there's an A13 inside the display, where's the apple tv+ support?
@bmastenbrook M1 Ultra Mac Studio starts at $3999.

CALLED IT

Studio Display at $1599 ImageImage
@bmastenbrook March 18th
And that's a wrap.

I've already seen a request for me to review it. I have zero contacts with Apple.

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More from @IanCutress

Feb 17
#IntelInvestorMeeting Thread - keynote presentations

I think someone exported this starting video at 720p.
Looks like it's an actual event with people on site.
People were invited. One day, perhaps.
Read 118 tweets
Feb 15
Intel's call on Tower Semi acquisition is starting. #thread $INTC $TSEM @intel
Gelsinger
Thakur
+ CEO Tower on the call
Interesting to see what will be said. Intel Financial day in a couple of days here
Read 42 tweets
Jan 18
The annual @ieee_isscc #ISSCC22 conference is coming up next month and the presentation list is now live. Here are some of the talks I'm really looking forward to.

submissions.mirasmart.com/ISSCC2022/PDF/…

Session 2 is all CPUs, hoping to see if Intel says more about PVC and SPR 1/x
2/ This one is a bit out of left field. Intel is going to talk about ultra-low-voltage Bitcoin ASICs. The DS1 in this talk means there's going to be a demo of it (perhaps more than simulation work?)
3/ @tenstorrent is going to talk more about Wormhole, it's 3rd generation big 700mm2+ chip. Uses GDDR6 and 16 x 100 GbE for scale out - you can connect as many chips together in a 2D array to create the AI training chip you need with predicable on-chip/off-chip latency
Read 6 tweets
Nov 16, 2021
Looking at the two new Sunway papers up for the Gordon Bell. None of them are Exaflop on FP64, for clarification.

The Quantum paper showcases 1.2EF using FP32, 4.4EF using mixed, on 41.9M cores. No FP64.

The nuclear paper showcases 298PF using FP64 on 40.4M cores.
It's worth noting that the definition of 'core' is being stretched here. Each chip is listed as having 390 cores - that's 6 groups of (8x8 compute elements + 1 management element). The management element has 512-bit SIMD, unclear what the compute elements can do with vectors
I suspect the management element also acts as the front-end for the compute elements in compute element-only mode.

So what we're really counting here is just execution ports that aren't AGUs or L/S
Read 6 tweets
Apr 12, 2021
The guy who proposed the TAGE branch predictor back in 2006 (and invented other things) is now working at Intel.
The Intel Advanced Architecture Development Group (AADG) is responsible for creating the next leap in Microprocessor Design and the future of the x86 environment at Intel by helping to solve the ‘Innovator’s Dilemma’ when it comes to a new core design for Intel.
This dilemma can be simplified into finding the answers to questions like:
Read 8 tweets
Mar 24, 2021
Now I've had some time for the @Intel announcements yesterday to sink in, here's my brain dump.
A number of analysts were quite reserved when @PGelsinger joined Intel, stating that no matter what he did, we wouldn't see it for years. I said straight away that Pat can steer the intent of the company as soon as he sat in the seat. Today is a clear message
That being said, Intel last week is still the same as Intel today. Saying stuff doesn't mean much unless Intel does pivot, and it will take a few years to enable that pivot, but there will be a strong undercurrent of things to come throughout, with a continuous focus on 2023
Read 13 tweets

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