Locuza Profile picture
27 Aug, 4 tweets, 3 min read
Well, @FritzchensFritz got hands on a PS5 again and did some awesome die shots!
Vanilla Zen2:
flickr.com/photos/1305612…

PS5 CPU Core:
flickr.com/photos/1305612…

The custom Zen2 CPU for Sony is only modified on the FPU side, digital logic and everything else looks identical.

1/x ImageImage
The custom FPU is now quite a bit shorter, aligning with the µcode ROM block.
Overall core size goes down from ~2.82mm² to ~2.50mm².
Vanilla Zen2 is ~13% larger, respectively the PS5 core is ~11% smaller.
The FPU register file got some cuts, optically it looks about 1/4 smaller than on vanilla Zen2.
So instead of 160x 256-Bit regs it could be about 120x 256-Bit regs in total.
In terms of digital logic, I would direct to a previous "analysis":
Nachschlag auf gut Deutsch:
Zen2 Vanilla FPU = 0.773mm² (~56% larger vs. PS5)
Zen2 Custom FPU = 0.497mm² (~36% smaller)

As stated above, FP-Scheduler and Execution Logic 1&2 are likely the same, but Execution Logic 3&4 appear to have some cuts. ImageImage

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28 Aug
And @FritzchensFritz said, "Let there be light!" and there was light:
flickr.com/photos/1305612…

Now, that the world has an incredible high quality PS5 die shot, I revisit my previous annotations and some crucial aspects are different than I thought.


1/x 🧵
It was premature from me to claim that Sony likely cut the FP pipes from 256b to 128b based on totally dark rectangles.
I should have worded it with much more uncertainty, because some people, and reportings, take it sometimes as a fact.
The custom FPU on the PS5...

2/x
supports the same instructions as a vanilla Zen2 core (The 4700S is using the PS5 SoC):
bodnara.co.kr/bbs/article.ht…

Some parts of the execution logic and the FP-Scheduler appear to be the same.
And even the FP register file might be...


3/x
Read 28 tweets
19 Jul
A discussion and curiosity is resolved now.
Van Gogh, which is used by Valve's Steam Deck, has 4 UMCs.
I expected 4x 16-Bit (a memory channel under LPDDR5 is actually 16-Bit wide).
The official spec claimed 5.5 Gbps (dual-channel), which didn't made sense to me.
It got corrected
Valve claims now 4x 32-Bit (128-Bit) which fits to 4 UMCs.
It also means that as on Renoir/Cezanne, AMD is using a controller design with a 32-Bit granularity instead of 16-Bit channels.

Even 64-Bit LPDDR5 wouldn't have been bad for the Steam Deck specs but now bw looks great.
In comparison to current gen consoles, only from the GPU perspective, you get more GB/s per TeraFLOP.
A small comparison:
XSX: 46.09 GB/s per GPU TFLOP
XSS: 55.91 GB/s per GPU TFLOP
PS5: 43.58 GB/s per GPU TFLOP
Steam Deck: 53.72-85.94 GB/s per GPU TF
Read 6 tweets
7 Feb
This was a nightmare project to work on, with a frankenstein audio recording mash up but I can't muster the strength and necessary time to re-record+cut the thing again.

Topic and details are quite interesting though.
Summary pictures follow this thread.

1) Xbox Series X/S die shots scaled to relative true size.
(It's not super accurate though)
2) PS4&Xbox One die shots scaled to relative true size
3.) ^ with annotations

If people are curious about the PS4/Xbox One gen, I could make an extra video for them. ImageImageImage
1) PS4 Pro and Xbox One X die shots scaled to relative true size.
2) ^ with annotations

Again, if someone wants a deep dive on those chips, I could make a video on it. ImageImage
Read 21 tweets
2 Sep 20
Ahh damn it, I again didn't managed a super fast rambling video about Renoir vs. Tiger Lake.
So it's time for a picture thread with rambling, less than 30 minutes to go.
1/x
I really like the CPU engine from Intel.
Willow Cove has a massive amount of cache and should do over 20% better per clock than Renoir.
Under 15-30W I'm also sceptical how well the 8 cores on Renoir scale but the results are out there, I just didn't had the time to look.
2/x
IIRC some 3DMark results showed ~50% higher CPU scores on Renoir vs. Tiger Lake models but that would be totally okay.
For me the device will be mostly for browsing and some casual games, I rather take the better ST performance.
3/x
Read 30 tweets
1 Sep 20
I think even for a speed rambling video the time is too short with Ampere's presentation coming in less than three hours which is why a picture thread with my thoughs will follow.
Ampere vs. Big Navi.🔥
1/x
The specs with 5248 "CUDA cores" are already out there for the GTX3090.
@_rogame found the configuration of Navi21 from driver files, confirming that 40WGPs/80CUs/5120 "cores" will be used.
Bringing both close together in terms of FP32 throughput
2/x
If 84 SMs are the maximum configuration of the GA102 chip then 6 GPCs are fitting, with 14SM each.
With 6 GPCs we have 6 Rasterizer/Scan Converter = 96 Pixels per clock.
ROPs are tied to Memory Controllers, with 384-Bit we have 96 ROPs = 96 Pixels/clock
3/x
Read 20 tweets
24 Jul 20
Zen 2 (+1) part 6 analysis for laymen is done:


Comparing the sizes of CCX, L3$, L2$, Core and starting with the L3$ item/device inventory.
Images with crucial information follow this tweet.
1) Technical details and differences between Zen1 and Zen2
2) Zen1 CCX size of 44.11mm²
3) Zen2 CCX size of 31.39mm²
4) Zen1 L3 Cache size of 16.32mm²
5) Zen2 L3 Cache size of 16.82mm²:
6) Zen1 and Zen2 L3 Caches side by side, scaled to relative true size
Read 7 tweets

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