Thread by @azonenberg

Finally got a decent EM simulation on the SATA pairs done. Only took four days... seems I need to simplify it further still.

Let's take a look at the results.

Here's insertion loss. S21 (red), is the left pair going through the layer change, S43 (blue) is the right pair with no layer change.

Looks like the layer change is introducing some kind of impedance mismatch.

Neither one really has great return loss, but the pair with the layer change is definitely a lot worse.

TDR transform on the two pairs (different Y axis scales).

Seems to suggest that the impedance on the back layer pair is way high, which makes no sense at first because the stackup is symmetric land I have stitching vias everywhere I should...

This is interesting. Simulating just the BGA launch in isolation shows uniformly terrible S11 and fairly decent S33.

I wonder if there's something to be learned from this...

Wut?? TDR transform of S11 is showing about 75 ohm impedance for what should be a 100 ohm line/

Derp. Had port impedance set wrong. That would explain a lot.

S-parameters and TDR transform of the two pairs with corrected impedance. Makes a lot more sense now.

I'd like to tune both further but the graphs are plausible.