Story time! So yesterday a courier dropped off a package which was meant for next door. I accepted it, put it in the hallway, and notice it had the massive logo from my previous employer, Future. I thought it was odd, but I messaged my neighbour to collect it when they're in /1
2/ Neighbour comes over later today, I mention I left the company two weeks ago, and she says that she's just left the company too! The box was to put all the computer hardware in and send back. Turns out the company she worked for had been acquired by Future back in November
3/ So technically my neighbour and I worked at the same company for 4 months without realising. She had left because they cut the team from 12 down to 4, but also increased the workload. Found a better offer elsewhere.
4/ It's also worth noting at the same time I left, I know 2 other people that also left. This makes 3, plus me is 4. Seems to be a high amount of turnover.
But it's a small world...!
5/ For everyone waiting to hear about my next gig, I promise soon. Just finalizing paperwork and wanting to get _everything_ squared away before announcing. But it's already starting - meetings after meetings, and several flights booked for North America already
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The annual @ieee_isscc#ISSCC22 conference is coming up next month and the presentation list is now live. Here are some of the talks I'm really looking forward to.
Session 2 is all CPUs, hoping to see if Intel says more about PVC and SPR 1/x
2/ This one is a bit out of left field. Intel is going to talk about ultra-low-voltage Bitcoin ASICs. The DS1 in this talk means there's going to be a demo of it (perhaps more than simulation work?)
3/ @tenstorrent is going to talk more about Wormhole, it's 3rd generation big 700mm2+ chip. Uses GDDR6 and 16 x 100 GbE for scale out - you can connect as many chips together in a 2D array to create the AI training chip you need with predicable on-chip/off-chip latency
Looking at the two new Sunway papers up for the Gordon Bell. None of them are Exaflop on FP64, for clarification.
The Quantum paper showcases 1.2EF using FP32, 4.4EF using mixed, on 41.9M cores. No FP64.
The nuclear paper showcases 298PF using FP64 on 40.4M cores.
It's worth noting that the definition of 'core' is being stretched here. Each chip is listed as having 390 cores - that's 6 groups of (8x8 compute elements + 1 management element). The management element has 512-bit SIMD, unclear what the compute elements can do with vectors
I suspect the management element also acts as the front-end for the compute elements in compute element-only mode.
So what we're really counting here is just execution ports that aren't AGUs or L/S