Discover and read the best of Twitter Threads about #c64
Most recents (5)
As all of us head right into the #NewYear2023 together, ladies and gentlemen, I will reflect us back on my first FIVE (5) years on Twitter in regards of my own limited-color #pixelart palettes that I created during that time, from #AAP64 (2017) to #DGA16 (2022). 😊💖
🧵 (01/12)
🧵 (01/12)
October 10, 2017. The day that when I signed onto Twitter myself for the very first time, I immediately launched my very first-ever palette weighing in at just 64 colors.
It was called #AAP64, and it was a HUGE runaway success on my first three (3) days on Twitter!!! 🤯
(02/12)
It was called #AAP64, and it was a HUGE runaway success on my first three (3) days on Twitter!!! 🤯
(02/12)
Immediately riding the tsunami of sheer success on Twitter indeed, I forwarded ahead with my first 16-color palette that I had made that same 2017 year called #AAP16, which was simply designed for beginners who want to get their feet wet in the world of pixel artistry...
(03/12)
(03/12)
💥Day 1: Doom iCEBreaker Edition
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
An iCE40UP #FPGA is tiny, with just 5000 logic cells, but that didn't stop Sylvain Munaut from running Doom. The design uses a @1bitsquared iCEBreaker board with added SPI ram.
Watch:
Source: github.com/smunaut/doom_r…
@1bitsquared ⛵️Day 2: VexRiscv FPU
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
I've long wanted an FPGA-friendly #RISCV core with FPU. @SpinalHDL granted my wish this year by adding IEEE 754 support to VexRiscv. It now supports float and double with single-cycle FADD, FSUB, FMUL, and FMADD.
Source: github.com/SpinalHDL/VexR…
Thread: I promised to cover the rest of the hardware as well. Well, here is Part 2 of my #C64 #hardware.
Part 1 can be found here:
#C64hardware 1/
Part 1 can be found here:
#C64hardware 1/
Lets start with the EasyFlash. It is modern hardware designed by skoe.
skoe.de/easyflash/doku…
It has 1MiB of FLASH and you can upload CRT images with software to it using an SD2IEC or even a 1541 when you split the data.
#C64hardware 2/
skoe.de/easyflash/doku…
It has 1MiB of FLASH and you can upload CRT images with software to it using an SD2IEC or even a 1541 when you split the data.
#C64hardware 2/
It comes with software to create CRT bundles of software and create a menu to select the PRG you want. I have a SID collection on it...
#C64hardware 3/
#C64hardware 3/
Thread: I'm a little bit bored, so let's talk a while about my #C64 #hardware collection, shall we? This setup is my #C64 workhorse. It is a German C64C equipped with a car TFT, two 1541-II floppies and it came with a 4x kernal switch.
#C64hardware 1/
#C64hardware 1/
The kernal switch gives me access to three other kernals beside the original C= kernal: JiffyDOS, SpeedDOS Plus and EXOSv3.
#C64hardware 2/
#C64hardware 2/
The alternative kernals include nice stuff like F-key functions for listing discs and speedloaders. Although I'm told JiffyDOS is the best(tm) speedloader I tend to use EXOSv3 most. A PRG with 81 block is loaded in 6s instead of 53s!
#C64hardware 3/
#C64hardware 3/
Pen plotter symphony #plottertwitter
Box fitting, filling, time lapse #plottertwitter
Box fitting, white gel pen on black paper. I need to find a better way to pause/resume plots #plottertwitter 
