Especially once IBM's POWER chips start using chiplets again, I imagine an #OpenPOWER laptop chip becomes dramatically simpler to produce.
On that front, as recently as #POWER8, #IBM was using multiple dies as one processor...
On that front, as recently as #POWER8, #IBM was using multiple dies as one processor...
The DCM configuration on #POWER8 was an acronym for Dual Chip Module, whereas all #POWER9 chips have been SCM (Single Chip Module).
Although of the chiplet papers that @AdoredTV reads, he hasn't seen any @IBMPowerSystems authors:
Although of the chiplet papers that @AdoredTV reads, he hasn't seen any @IBMPowerSystems authors:
The network-on-interposer stuff is really interesting, and it would be interesting to see how it will work it's way into #PowerArchitecture.
Especially seeing as how the push from IBM seems to be toward generalizing CPU/CPU, CPU/GPU, and even CPU/Memory interconnects into one interface, what would the chiplet-chiplet interface look like?
@AdoredTV has speculated about Ryzen module configurations where the IO is delegated to a separate die from the cores.
With @IBMPowerSystems push for higher IO performance, I don't see that as an option for the POWER chip line.
With @IBMPowerSystems push for higher IO performance, I don't see that as an option for the POWER chip line.
