oh no! boards arrived. time to figure out if my clone of the ultra-rare Ad Lib MCA works or not. wish me luck! 
first check: will it fit the MCA socket? why yes, yes it does.
second check, supply voltages ok? no parts soldered in yet.
gonna socket all the chips just in case. good thing I have this designer kit assortment.
validating the PAL. took me a while to find which of my programmers support this device
this is enough of the circuit to provide the card ID. let's see if the BIOS can find and configure it.
hmmm, it freezes at this point.
looks like it's crashing the bus somehow.
current status 😅
so there's some odd stuff going on. POS register 102 bit zero is supposed to be the card enable. here the PC writes a 00 to it, but the CDEN (card enable) output of the 82C611 goes high! this shouldn't happen.
bus crash happens because the 82c611 is pulling CD_CHRDY low, like it wants infinite wait states. this is triggered by the ADPRDY input somehow going low. it's tied to a few other pins (TEST1/TEST2/DS16#,ERROR#) and to a 10K pullup. all these pins are inputs. 🤦♂️
let's see what happens when each input gets its own pullup.
ohhhhhh yeah! it's getting detected correctly and not crashing!
also looks like writes to 0x388 are going through! i'm doing this from qbasic lol. CDSEL is driven from the PAL so it looks like it's decoding the addresses correctly.
good progress today. think i'll solder in the Yamaha parts and the analog signal chain tomorrow. then bring up the rest of the card!
soldered up the analog portion. guess who forgot to order the right volume potentiometer 🤪
no sound. 😑i'm looking at the timing and it seems like the address line A0 going into the YM3812 has a negative hold time! probably need to modify the PAL to extend A0 a bit. 🤔
the PAL has one unused signal that i've been wondering about, ADL#. the signal is supposed to pulse low to latch the address. however the CDSEL signal (according to the 82c611 datasheet) is only qualified by the address pins and not ADL#.
however i think the Ad Lib folks mistakenly qualified it with ADL# as well. this would shorten the width of the YM3812 chip select pulse but then meet the A0 hold time spec.
i could try to do that too, but that violates the YM3812 timing spec for the RD# pulse width. you just can't win. i could also latch A0 on the rising edge of CDSEL. i'm using a registered PAL so that could work...
well that did not work. i need to think about this some more.
here's a good illustration of the issue. the A0 line changes while the chip select is asserted. not good! but if i can latch the A0 line when ADL# asserts, i think it'll fix it.
so i can't use registered mode because it requires pin 11 as dedicated OE. but what if i build a latch just using gates, like this:
sim looks promising.
and the real thing looks pretty good! plenty of setup and hold.
and yet the card doesn't work. no sound. 🤔
looks like something is wrong with the data buffers going to the YM3812. that is not a strong 1! could also be two buffers trying to drive at the same time
could only be the CHIPS chip. it was already acting funny during card setup mode. i guess I'll try swapping it out.
ohhh yeah! we've got first sounds out of the Plaid Bib! 🔊
but the official test program doesn't work. probably something wrong with the read cycle. back to the logic analyzer again. 😅
implemented this algorithm in QBASIC, and it detects the card! this is VERY odd.
think i figured it out. detect routine sets the YM3812 timer to 0xFF so it rolls over quick and sets the flag, which is then detected. *however* for some reason bit 3 on my card is stuck low, leading the value 0xF7 to get written. thus the flag gets set after a much longer delay!
trying a current limit resistor so the 82c611 loses every fight, at least for D3.
yeah that wasn't it. turns out it was a minor oversight on the the OEa# pin was tied on the '244 buffer. it should have been tied to pin 19, not to ground! this forced a fixed value onto the low nibble of the data bus.
just one little wire........
heavy breathing intensifies.......
turn on sound for this one folks 😂
time to fix the volume control now that the parts arrived.
looking sharp.
i need to replace the 82C611 chip with something easier to get, like a CPLD. but first i have to write some verilog. this won't be a full replacement, just enough to get the Plaid Bib working.
it's very important to write good test benches. why does it have to be so boring though?!
doing a little adapter board. this will let me prototype the CPLD-based Plaid Bib without having to spin the entire card.
finally got around to this project again. the adapter boards came in, but I need to assemble one now.
i didn't order a stencil, but i found one from another project with the right footprint for the CPLD
now for a @GregDavill style macro photo of the solder paste.
which one is the pin 1 mark? 😑
i think pin 1 is the small dot.
soldered up! now to see if Jay Tag works 😅
ohh yeah, it's working!
bare bones configuration. time to see if this will show up on the MCA bus.
ohh yeah, the card ID shows up!
still some strange issues going on, and it's not particularly stable. i will need to spend some quality time with a logic analyzer.
so i pulled the card, and i still get these errors when i boot the PS/2. at least i can hit F1 and it can finish booting. 😑
also i forgot to bring all the address lines over to the CPLD. this should help.
address decoding works, but sometimes the logic analyzer gives me glitches. the analog voltage here is only 0.7v. i think i need to improve the grounding.
to help with troubleshooting i pared the verilog code back to just the basic address decoder. i'll slowly add in the pieces one at a time, testing at every step.
ok, after adding stuff back very carefully i got it to show up properly! you can see that the BIOS has enabled the card and programmed the POS bytes correctly.
it works now!
time to add the analog circuitry to make sure it actually makes sound.
it makes sound! how exciting. 😁
the CPLD version. cleaned up a bunch of extra chips too. now what do i do with all the extra space?
almost forgot to ask: anyone have a PS/2 model 70, 80, or 90 who can test this card for me? (386 CPUs and above) people with a logic analyzer will get priority. more so if you can program Xilinx CPLDs (xc3sprog, etc). and even more so if you're in silicon valley.
