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Peter Todd @peterktodd
, 23 tweets, 4 min read Read on Twitter
Some thoughts on proofs-of-time, as I've been spending a bunch of time looking at ASIC design lately...

0) As we know, if I have a significantly faster proof-of-time than others, I have a potential advantage.
1) A proof-of-time is essentially restricted by the latency from input to output. At the low level, that latency can be measured by the maximum number of logic gates - the critical path. Often adding more gates can *decrease* that latency (e.g. carry-lookahead adders).
2) It may also be possible to decrease that latency by making circuits unreliable; to combat the unreliability, you'd add parallelism until at least one attempt worked.
3) A closely related approach is parallelized verification: have a single fast path that attempts to do the computation, with a larger set of parallelized verifiers that determine if the result was in fact correct. Failure could then trigger a switch to a parallel unit.
4) If there are multiple different implementations of a calculation possible, with each having data-dependent latency, you can run all implementations in parallel and simply pick the result that was calculated first. An async logic approach could work well here.
5) Transistors switch faster at lower temperatures. Normally keeping chips cool is a major challenge, but a proof-of-time inherently has a small amount of hardware in use. Enter low-duty cycle impls: units calculate very briefly at high wattage, then switch off to cool down....
...relying on the thermal mass of the chip to avoid overheating. Almost arbitrarily high power density can be achieved by simply throwing more hardware at the problem, which reduces latency by allowing the chips to be physically smaller...
...and by allowing multi-die stacked designs to be used that would otherwise overheat (this is why FLASH memory is basically the only type of chip that has dozens of transistor layers).
6) Hardware can be one-shot: it'd be feasible to use current densities so high that the hardware is actually permanently damaged by a computation, and thrown away at the end. While bad PR, $$$ spent on trashed electronics is not economically different than $$$ spent on power.
8) So in summary, an optimal proof-of-time implementation at a large scale may be an extension of a chip fab. Rather than fan noise, you'd hear the whirring sound of FOUPs filled with wafers being shuttled in from the fab proper once a minute....
...with each arrival triggering a blur of robotic movement as the dozens of wafers inside are extracted and placed on the belts, finishing just in time for a brief break while the empty FOUP left.
The belts however never stopped. Officially known by some corporate-speak acronym, informally the staff called them the "Killing Lines"; surrounded by robots on both sides, the wafers on the belts were steadily marching to their doom.
Exactly how far a wafer got was a matter of chance. But when the time came, it'd be picked up and placed on a cold plate. Bathed in dry nitrogen, the thin wafer took a few seconds to cool down to a chilly -170°C, all while a distant popping got closer.
With thermal equilibrium reached down came the top half of the cold plate. A curious device, at once a heavy duty piece of industrial machinery with thick cables fit for powering a spot welder. Yet also lined with thousands of tiny electrical contacts, carefully aligned by laser.
As the popping gets closer the first flicker of power comes on. Just an initial self-test; it's a good wafer with only a few bad spots, automatically mapped out and ignored. Standby.

A few precious kilobytes stream in from the wafer's neighbor at the speed of light; it's dying sound will come much later. In the center of the wafer, die #0 starts a lifetime of work, it's billions of transistors switching on and off for a short eternity....
....taking the time to send the next in line, die #1, a backup of the calculations as each eon of computation passes. But at a more human scale, eternity is over quick. As its chilly paradise heats up, and electrons themselves knock atoms out of place, something goes wrong.
Amongst the billions of transistors, one finally gives out. As the errors cascade - garbage in, garbage out - one last backup is sent to die #1. It doesn't make sense though; the sums don't add up.
But death was always expected. So #1 unceremoniously triggers its predecessor's electronic euthanasia and continues on, redoing that last eon of calculations.
Of course, it too suffers the same fate. As do the other 467 dies on that wafer, save for a dozen at the very end who didn't even get their chance at life - the wafer itself cracked in half a bit prematurely from the thermal stress.
To you those eons of calculation pass by in just a few seconds. Power cables shudder and whine, a loud pop, and then it's the next wafer's turn one station down.
As the cover opens automatically one last robot robot arm moves into position. But it's not as high tech as the rest: armed with some bristles it simply sweeps the now dead wafer into the trash chute.

Of course, look on the bright side: while that story was fun to write, if that bit of cypherpunk fiction were ever actually true Chia would have to be a staggering success: wafers are worth thousands of dollars each. :)
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