Thread by @arbiterofbits

Yeah!

Xilinx has a few app notes: xapp495 and xapp460.

A few more words: tmds is 8b/10b encoded. That means for every 8 bit value there is a corresponding 10 bit value (a 1 to 1 look up table).

It uses LVDS (low voltage differential signaling) to transmit the data 1/n

In the case of HDMI it actually sends the clock as well (which isn't always the case for high-speed links - often they do clock recovery, but that's a topic for another day).

So there are 8 wires, that represent 4 unique signals: Red, Green, Blue, Clock 2/n

(note: I'm using Red/Green/Blue for simplicity, the HDMI standard supports a number of different color spaces)

For every clock rising edge, we set the values on the "data bus" (red, green, blue).

We use a differential buffer to change the CMOS level to a LVDS level 3/n

So ... Good opportunity to talk about clock vs data.

For every clock edge, there is actually 10 bits of data. That's because we send the "raw" clock that represents the 10 bit value for each edge vs the "line clock" that represents 10x that speed.

4/n

Every pixel clock, we get 3 red, green, blue values. We then serialize them at 10x the speed to send over the HDMI cable. 5/n

So we have a SERDES on both ends that run at 10x the pixel clock.

RGB + clk into the OSERDES

RGB + clk out of the ISERDES.

6/n

Here is a simplified timing diagram and block diagram for components.

Making sense?

Standing by for more questions!

7/7