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Here is part two of Intel's newly published patent list. Follow the thread!

Patent: Controller for locking of selected cache regions - Intel

More details: freepatentsonline.com/20190340123.pdf
Patent: Subsystem-based SoC integration - Intel

Subsystem abstractions for the next-gen Intel SoCs.

More details: freepatentsonline.com/20190340313.pdf
Patent: Innovative Fan-Out Panel Level Package (FOPLP) warpage control - Intel

More details: freepatentsonline.com/20190341356.pdf
Patent: Thermal management solutions for stacked integrated circuit devices using unidirectional heat transfer devices - Intel

Unidirectional heat transfer device: A very pretty way to call a Peltier module in Foveros...

More details: freepatentsonline.com/20190343017.pdf
Patent: Memory-based software barriers - Intel

More details: freepatentsonline.com/20190340018.pdf
Patent: Dynamic presentation of interconnect protocol capability structures - Intel

More details: freepatentsonline.com/20190340148.pdf
Patent: Side mounted interconnect bridges - Intel

Vertical EMIB for 3D integration... Just Wow!

More details: freepatentsonline.com/20190341349.pdf
Patent: Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch - Intel

More details: freepatentsonline.com/20190341300.pdf
Patent: Low cost package warpage solution - Intel

More details: freepatentsonline.com/20190341271.pdf
Patent: Microelectronic device with embedded die substrate on interposer - Intel

More details: freepatentsonline.com/20190341351.pdf
Patent: Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory - Intel

More possibilities around Foveros...

More details: freepatentsonline.com/20190341371.pdf
Patent: Apparatus and method for hierarchical adaptive tessellation - Intel

More details: freepatentsonline.com/20190340812.pdf
Patent: Configuration of a programmable device - Intel

More details: freepatentsonline.com/20190342141.pdf
Patent: Method, apparatus and system to interconnect packaged integrated circuit dies - Intel

More details: freepatentsonline.com/20190341372.pdf
Patent: An apparatus for semiconductor package inspection - Intel

More details: freepatentsonline.com/20190339212.pdf
Patent: Integrated circuit comprising multiple channels with integrated bypass capacitors and photodiodes - Intel

More details: freepatentsonline.com/20190339122.pdf
Patent: Systems, methods, and apparatuses for tile diagonal - Intel

More details: freepatentsonline.com/20190339972.pdf
Patent: Achieving consistent read times in multi-level non-volatile memory - Intel

More details: freepatentsonline.com/20190332277.pdf
Patent: Dynamic core selection for heterogeneous multi-core systems - Intel

More details: freepatentsonline.com/20190332158.pdf
Patent: Scalable bandwidth non-volatile memory - Intel

More details: freepatentsonline.com/20190332278.pdf
Patent: Method and apparatus to process SHA-2 secure hashing algorithm - Intel

More details: freepatentsonline.com/20190332378.pdf
Patent: Ground via clustering for crosstalk mitigation - Intel

More details: freepatentsonline.com/20190333848.pdf
Patent: Address range based in-band memory error-correcting code protection module with syndrome buffer - Intel

More details: freepatentsonline.com/20190332469.pdf
Patent: Transistor with dynamic threshold voltage for low-leakage standby and high speed active mode - Intel

More details: freepatentsonline.com/20190334010.pdf
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