Thread by @slightlylate

Meet the $100 phone! This is the Moto C Plus: m.gsmarena.com/motorola_moto_…

It's currently on offer on Flipkart (homepage, above-the-fold):

The SoC is quad-core, but let's dig into what that means in practice:

mediatek.com/products/smart…

Because this is fab'd on the (zomg bad) 28nm process, thermal concerns keep it clocked to 1.3ghz

Which wouldn't be so bad if it had any cache or if the architecture was modern.

No such luck! All 4 cores are last-of-the-in-order-design A53s.

And experience tells me that when L2/L3 aren't called out by manufacturer, it's because there isn't any to speak of: notebookcheck.net/Mediatek-MT673…

So how should you think about the A53?

First, note the phrase "high efficiency" in the marketing material: developer.arm.com/products/proce…

This was not designed to be a speed demon. It was, however, the first core design for Androids that was available in 64-bit...

...this mattered a LOT in 2014 when Android handset makers got their butts handed to them by Apple over 64-bit: theverge.com/2014/8/27/6076…

But they did it badly. 28nm was the new hotness -- as it turned out literally.

Electron-voltage leakage on the 28nm process was *bad*.

This wasn't entirely unexpected, but the size of the problem on 28nm surprised most everyone. Couldn't frequency scale as a result.

...and *that* mattered because costs for SoCs have a lot to do with die sizes...and the easiest thing to cut is cache.

Consumers don't know to look for L2/L3 cache sizes on the tin. How would you even start to explain cache coherence to a punter?

So you don't; you sell core counts.

...and core counts are a lie. DVFS keeps most cores are spun down most of the time. I go into it a tiny bit here:

But it's really hard to overstate the impact of code and data locality. A bigger cache means you go to main memory less.

Check out the chart here for context: anandtech.com/show/9837/snap…

You *badly* want to be in that low/left end of the curve. The easiest way to get that is a bigger cache so more programs do more of the time

...yet, mostly for cost and marketing reasons, nearly all Android-ecosystem SoCs are CPU poor. Many have tiny L2 and little (if any) L3.

MEANWHILE IN CUPERTINO:

en.wikipedia.org/wiki/Apple_A9
en.wikipedia.org/wiki/Apple_A10
en.wikipedia.org/wiki/Apple_A11

Yes, you're reading that right: between the A10 and the A11, Apple went from 3MB L2/4MB L3 to *8MB L2*

For a sense of scale:

norvig.com/21-days.html#a…

people.eecs.berkeley.edu/~rcs/research/…

So back to our $100 phone. The slow-clocked (1.3Ghz) A53 cores are missing _any_ discernible cache. What does that mean?

It means that anything that isn't a tight loop on a small amount of data is going to suffer a main-memory read.

...and main-memory reads are 200x more expensive than local (L1) reads. Need that data to keep doing work? Tough luck.

These situations are called "stalls" or "waits"; CPU is spun up, but it's not retiring instructions (doing work): en.wikipedia.org/wiki/Wait_state

...which means that one of the worst effects of the cores-not-caches tradeoff in this phone is that it loses *power efficiency* too.

The best trade in mobile CPU design today is to swap caches for cores (looking at you @qualcomm, @SamsungSemiUS, & @MediaTek)

So how slow is the @MediaTek MT6737? Lets go to the film!

Here are some devices built with this chip: kimovil.com/en/list-smartp…

...and they all score like this:

browser.geekbench.com/v4/cpu/4478849

This is 8-9x slower than the iPhone 8: browser.geekbench.com/ios_devices/51

These are both devices you can buy new, today.