This thread will contain all new SA-1 chip findings
Data verified on real hardware. Emulator authors should definitely keep in mind this information for updating the SA-1 emulation later.
$50-$5F is BW-RAM mirror. That means everything between banks $40 and $5F is BW-RAM. Does that mean SA-1 could map up to 2 *MEGABYTES* of RAM?
There is no info about how to activate 256KB of BW-RAM, but please make $00:FFD8 = #$08 give 256 KB for SA-1 and not 0 KB currently.
Only banks $40-$4F and $60-$6F are mapped on SNES side.
Virtual memory allows reading only two or four bits of the BW-RAM, useful for storing packed 4bpp or 2bpp pixels.
The circuit responsible for the SA-1 bit stream feature has a few oddities.
That means ROM addresses like $00:8001 will be read as $00:8000 instead.
2) The address expects the actual memory map.
However regions that does not map to ROM will just mirror to bank 0 instead
Even worse, for banks $40-$7F, *everything* is bank 0 mirror (LoROM!)
Banks $C0-$FF works as expected (HiROM).
In other words, divide the memory map in 32 KB blocks.
$00-$3F; $80-$BF: LoROM ($8000)
Everything else: Mirror to bank 0.
You can enable FastROM on a SA-1 ROM.
What happens? The SA-1 chip is paused whenever SNES attempts a fast ROM reading, however it does not crash. The system is smart enough to allocate all of its I/O resources and hand to the SNES system.
This is extremely clever and even more if you consider that's only possible with the chip monitoring changes to the $420D register.
Also verified that DMA and HDMA doesn't affect SA-1 speed even on FastROM area.